OTBN Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 12.000s 45.753us 0 1 0.00
V1 single_binary otbn_single 18.000s 86.221us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 42.694us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 63.916us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 83.298us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 17.102us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 6.000s 40.174us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 63.916us 1 1 100.00
otbn_csr_aliasing 4.000s 17.102us 1 1 100.00
V1 mem_walk otbn_mem_walk 23.000s 3.155ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 14.000s 852.070us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 29.000s 304.745us 0 1 0.00
V2 multi_error otbn_multi_err 38.000s 608.113us 0 1 0.00
V2 back_to_back otbn_multi 37.000s 166.931us 0 1 0.00
V2 stress_all otbn_stress_all 6.483m 2.075ms 0 1 0.00
V2 lc_escalation otbn_escalate 7.000s 17.920us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 6.000s 60.207us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 15.000s 45.285us 0 1 0.00
V2 alert_test otbn_alert_test 8.000s 18.630us 1 1 100.00
V2 intr_test otbn_intr_test 5.000s 51.062us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 5.000s 32.153us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 5.000s 32.153us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 42.694us 1 1 100.00
otbn_csr_rw 4.000s 63.916us 1 1 100.00
otbn_csr_aliasing 4.000s 17.102us 1 1 100.00
otbn_same_csr_outstanding 5.000s 14.805us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 42.694us 1 1 100.00
otbn_csr_rw 4.000s 63.916us 1 1 100.00
otbn_csr_aliasing 4.000s 17.102us 1 1 100.00
otbn_same_csr_outstanding 5.000s 14.805us 1 1 100.00
V2 TOTAL 6 11 54.55
V2S mem_integrity otbn_imem_err 8.000s 57.664us 0 1 0.00
otbn_dmem_err 5.000s 30.062us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 9.000s 235.789us 0 1 0.00
otbn_controller_ispr_rdata_err 20.000s 351.883us 0 1 0.00
otbn_mac_bignum_acc_err 12.000s 55.060us 0 1 0.00
otbn_urnd_err 6.000s 28.914us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 5.000s 10.129us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 6.000s 13.940us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 10.000s 49.531us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 2.917m 1.122ms 1 1 100.00
otbn_tl_intg_err 16.000s 361.059us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 22.000s 775.337us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 12.000s 45.753us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 5.000s 30.062us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 8.000s 57.664us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 16.000s 361.059us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 7.000s 17.920us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 8.000s 57.664us 0 1 0.00
otbn_dmem_err 5.000s 30.062us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 60.207us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.129us 1 1 100.00
otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 18.000s 86.221us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 8.000s 57.664us 0 1 0.00
otbn_dmem_err 5.000s 30.062us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 60.207us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.129us 1 1 100.00
otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 7.000s 17.920us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 8.000s 57.664us 0 1 0.00
otbn_dmem_err 5.000s 30.062us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 60.207us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.129us 1 1 100.00
otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 18.000s 86.221us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 6.000s 21.808us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 6.000s 40.124us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 21.000s 334.091us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 21.000s 334.091us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 8.000s 34.455us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 7.000s 102.432us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 13.000s 160.897us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 13.000s 160.897us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 6.000s 10.067us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 18.000s 86.221us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 18.000s 86.221us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 18.000s 86.221us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 37.000s 166.931us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 18.000s 86.221us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 18.000s 86.221us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 12.000s 90.707us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 18.000s 86.221us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 2.917m 1.122ms 1 1 100.00
V2S TOTAL 9 20 45.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.850m 1.462ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 22 41 53.66

Failure Buckets