ROM_CTRL/32KB Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	3.870s	669.955us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.790s	174.971us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.170s	374.290us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.430s	372.009us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	3.550s	556.573us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	3.410s	967.418us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.170s	374.290us	1	1	100.00
		rom_ctrl_csr_aliasing	3.550s	556.573us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.470s	174.436us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.710s	557.904us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.060s	1.263ms	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	15.180s	1.283ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.110s	312.953us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.480s	126.926us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	4.790s	215.450us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	4.790s	215.450us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.790s	174.971us	1	1	100.00
		rom_ctrl_csr_rw	3.170s	374.290us	1	1	100.00
		rom_ctrl_csr_aliasing	3.550s	556.573us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.020s	631.943us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.790s	174.971us	1	1	100.00
		rom_ctrl_csr_rw	3.170s	374.290us	1	1	100.00
		rom_ctrl_csr_aliasing	3.550s	556.573us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.020s	631.943us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	17.100s	1.140ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.160m	1.030ms	0	1	0.00
		rom_ctrl_tl_intg_err	23.790s	336.955us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.160m	1.030ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.160m	1.030ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.160m	1.030ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.160m	1.030ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	3.870s	669.955us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	3.870s	669.955us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	3.870s	669.955us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	23.790s	336.955us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
		rom_ctrl_kmac_err_chk	9.110s	312.953us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	43.530s	5.156ms	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	17.100s	1.140ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.160m	1.030ms	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	3.011m	6.369ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.20363579305837133053198055071589231989458507661576692839432679248617145631588
      Line 92, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 5156221966 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 5156221966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.56502463693121744431381659490563129527195366557074222587957201065016022639726
      Line 185, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 26859609ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 26859609ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 26859609ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))