ROM_CTRL/64KB Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.420s	483.670us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.320s	1.083ms	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.530s	384.303us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.670s	1.066ms	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.790s	555.845us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.060s	225.906us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.530s	384.303us	1	1	100.00
		rom_ctrl_csr_aliasing	6.790s	555.845us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.850s	210.488us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.390s	764.980us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	12.320s	1.066ms	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	18.930s	1.050ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.460s	1.060ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	10.230s	1.033ms	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.100s	440.899us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.100s	440.899us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.320s	1.083ms	1	1	100.00
		rom_ctrl_csr_rw	5.530s	384.303us	1	1	100.00
		rom_ctrl_csr_aliasing	6.790s	555.845us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.630s	217.697us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.320s	1.083ms	1	1	100.00
		rom_ctrl_csr_rw	5.530s	384.303us	1	1	100.00
		rom_ctrl_csr_aliasing	6.790s	555.845us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.630s	217.697us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	39.380s	6.631ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	7.191m	1.309ms	0	1	0.00
		rom_ctrl_tl_intg_err	1.460m	871.662us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	7.191m	1.309ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	7.191m	1.309ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	7.191m	1.309ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	7.191m	1.309ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.420s	483.670us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.420s	483.670us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.420s	483.670us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.460m	871.662us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
		rom_ctrl_kmac_err_chk	16.460s	1.060ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.432m	4.962ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	39.380s	6.631ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	7.191m	1.309ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.834m	9.321ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.25123107751128530701947149153047222193916763423396426032698044680616097597669
      Line 164, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 16530502ps failed at 16530502ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 289: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 16540603ps failed at 16540603ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'