RV_TIMER Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.600s	20.908us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.630s	120.772us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.660s	19.272us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.390s	560.431us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.660s	65.423us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.850s	31.918us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.660s	19.272us	1	1	100.00
		rv_timer_csr_aliasing	0.660s	65.423us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	8.300s	24.661ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.500s	3.417ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.259m	148.274ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.259m	148.274ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.980s	1.472ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.570s	47.668us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.610s	24.076us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.170s	51.311us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.170s	51.311us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.630s	120.772us	1	1	100.00
		rv_timer_csr_rw	0.660s	19.272us	1	1	100.00
		rv_timer_csr_aliasing	0.660s	65.423us	1	1	100.00
		rv_timer_same_csr_outstanding	0.640s	101.671us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.630s	120.772us	1	1	100.00
		rv_timer_csr_rw	0.660s	19.272us	1	1	100.00
		rv_timer_csr_aliasing	0.660s	65.423us	1	1	100.00
		rv_timer_same_csr_outstanding	0.640s	101.671us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.060s	131.142us	1	1	100.00
		rv_timer_tl_intg_err	1.030s	161.289us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.030s	161.289us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.650s	20.989us	1	1	100.00
V3	max_value	rv_timer_max	0.750s	29.957us	1	1	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	17.200s	11.583ms	1	1	100.00
V3		TOTAL			3	3	100.00
		TOTAL			19	19	100.00