SPI_DEVICE/1R1W Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.538m	166.797ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.840s	49.198us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.180s	468.947us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.110s	9.334ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.980s	400.582us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.900s	120.723us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.180s	468.947us	1	1	100.00
		spi_device_csr_aliasing	14.980s	400.582us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.760s	10.332us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.710s	58.609us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.870s	41.491us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	5.278us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	10.510us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.750s	41.021us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.750s	41.021us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	8.880s	10.921ms	1	1	100.00
		spi_device_tpm_sts_read	0.730s	123.869us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	11.850s	13.103ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.760s	74.624us	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.910s	27.979ms	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.910s	27.979ms	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.670s	207.372us	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.670s	207.372us	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.670s	207.372us	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.670s	207.372us	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.670s	207.372us	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.020s	5.428ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.690s	66.515us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.690s	66.515us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.690s	66.515us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.780s	179.238us	1	1	100.00
		spi_device_read_buffer_direct	6.050s	5.756ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.690s	66.515us	1	1	100.00
		spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.248m	27.998ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.260s	250.735us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.260s	250.735us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.538m	166.797ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	53.370s	6.801ms	1	1	100.00
V2	stress_all	spi_device_stress_all	11.704m	451.677ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.730s	35.977us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.790s	15.401us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.310s	83.206us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.310s	83.206us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.840s	49.198us	1	1	100.00
		spi_device_csr_rw	2.180s	468.947us	1	1	100.00
		spi_device_csr_aliasing	14.980s	400.582us	1	1	100.00
		spi_device_same_csr_outstanding	2.940s	1.781ms	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.840s	49.198us	1	1	100.00
		spi_device_csr_rw	2.180s	468.947us	1	1	100.00
		spi_device_csr_aliasing	14.980s	400.582us	1	1	100.00
		spi_device_same_csr_outstanding	2.940s	1.781ms	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.040s	66.097us	1	1	100.00
		spi_device_tl_intg_err	9.560s	775.937us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.560s	775.937us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	57.250s	7.250ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.89781531779817497631152677632480764206429450240787610835899592902765830461760
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4557846 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[75])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4557846 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4557846 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[971])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.15343845502038106508857588453453627444764241293481049022216827397484764448069
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   8280161 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbf7566 [101111110111010101100110] vs 0x0 [0])
        UVM_ERROR @   8305161 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2c2dda [1011000010110111011010] vs 0x0 [0])
        UVM_ERROR @   8367161 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfef042 [111111101111000001000010] vs 0x0 [0])
        UVM_ERROR @   8391161 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4c5a08 [10011000101101000001000] vs 0x0 [0])
        UVM_ERROR @   8430161 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd88c6 [11011000100011000110] vs 0x0 [0])