SPI_HOST Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	25.000s	1.456ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	42.950us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	33.939us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	1.020ms	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	55.495us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	37.166us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	33.939us	1	1	100.00
		spi_host_csr_aliasing	2.000s	55.495us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	19.861us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	59.803us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	37.192us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	192.738us	1	1	100.00
		spi_host_error_cmd	2.000s	19.011us	1	1	100.00
		spi_host_event	13.000s	1.183ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	182.009us	1	1	100.00
V2	speed	spi_host_speed	4.000s	182.009us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	182.009us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	121.741us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	30.245us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	182.009us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	182.009us	1	1	100.00
V2	duplex	spi_host_smoke	25.000s	1.456ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	25.000s	1.456ms	1	1	100.00
V2	stress_all	spi_host_stress_all	12.000s	838.379us	1	1	100.00
V2	spien	spi_host_spien	8.000s	1.604ms	1	1	100.00
V2	stall	spi_host_status_stall	47.000s	1.353ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	56.568us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	192.738us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	15.097us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	33.294us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	39.087us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	39.087us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	42.950us	1	1	100.00
		spi_host_csr_rw	2.000s	33.939us	1	1	100.00
		spi_host_csr_aliasing	2.000s	55.495us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	28.331us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	42.950us	1	1	100.00
		spi_host_csr_rw	2.000s	33.939us	1	1	100.00
		spi_host_csr_aliasing	2.000s	55.495us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	28.331us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	261.943us	1	1	100.00
		spi_host_sec_cm	3.000s	74.945us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	261.943us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	8.867m	23.084ms	1	1	100.00
		TOTAL			26	26	100.00