SRAM_CTRL/MAIN Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	33.830s	446.833us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.900s	41.298us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.890s	19.477us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.110s	45.188us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.800s	30.278us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.140s	365.344us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.890s	19.477us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	30.278us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.248m	28.140ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	49.950s	2.023ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.985m	8.289ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.235m	4.228ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	9.251m	50.567ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.634m	8.403ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	51.730s	13.512ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.305m	6.035ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.010s	19.568ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.563m	16.885ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	33.100s	8.135ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.520s	3.082ms	1	1	100.00
		sram_ctrl_throughput_w_readback	15.040s	798.098us	1	1	100.00
V2	regwen	sram_ctrl_regwen	14.204m	64.885ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.100s	343.917us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.487m	95.373ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.980s	19.390us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.520s	149.904us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.520s	149.904us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.900s	41.298us	1	1	100.00
		sram_ctrl_csr_rw	0.890s	19.477us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	30.278us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.720s	33.185us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.900s	41.298us	1	1	100.00
		sram_ctrl_csr_rw	0.890s	19.477us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	30.278us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.720s	33.185us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.290s	15.371ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.900s	7.193us	0	1	0.00
		sram_ctrl_tl_intg_err	1.340s	131.063us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.900s	7.193us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.340s	131.063us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	14.204m	64.885ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	14.204m	64.885ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.890s	19.477us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.305m	6.035ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.305m	6.035ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.305m	6.035ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	51.730s	13.512ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.900s	13.399ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.290s	15.371ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.450s	664.473us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	33.830s	446.833us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	33.830s	446.833us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.305m	6.035ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.900s	7.193us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	51.730s	13.512ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.900s	7.193us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.900s	7.193us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	33.830s	446.833us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.900s	7.193us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	42.290s	1.470ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.112331493044012198898869509363476645433348601451377178611825964846685595114422
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7192882 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7192882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---