SRAM_CTRL/RET Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.980s	454.775us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	62.776us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.650s	38.983us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.610s	482.264us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.660s	41.066us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.050s	379.884us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.650s	38.983us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	41.066us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.790s	535.131us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.400s	384.742us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	5.608m	101.018ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.153m	19.254ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	42.960s	6.696ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.173m	20.459ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.800s	3.996ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.370m	26.559ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.550s	611.117us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.070m	20.989ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	8.420s	76.154us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	10.280s	93.688us	1	1	100.00
		sram_ctrl_throughput_w_readback	3.950s	114.461us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.556m	16.773ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.780s	82.304us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.767m	49.750ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.750s	40.217us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.890s	25.328us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.890s	25.328us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	62.776us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	38.983us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	41.066us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	19.771us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	62.776us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	38.983us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	41.066us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	19.771us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.120s	403.189us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.870s	1.795us	0	1	0.00
		sram_ctrl_tl_intg_err	1.150s	110.820us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.870s	1.795us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.150s	110.820us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.556m	16.773ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.556m	16.773ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.650s	38.983us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.370m	26.559ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.370m	26.559ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.370m	26.559ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.800s	3.996ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.770s	35.403us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.120s	403.189us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.010s	39.861us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.980s	454.775us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.980s	454.775us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.370m	26.559ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.870s	1.795us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.800s	3.996ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.870s	1.795us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.870s	1.795us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.980s	454.775us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.870s	1.795us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.709m	2.978ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.20034698063686123159026867040364790592195151716464532469245308552701265839463
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1795329 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1795329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.55520506467198318874001522828487649782292013430261047808223630319568977664988
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 379884375 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @ 379884375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---