UART Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.550s	764.882us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.740s	37.806us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.760s	20.882us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.410s	294.151us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.860s	40.419us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.930s	33.903us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.760s	20.882us	1	1	100.00
		uart_csr_aliasing	0.860s	40.419us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	16.070s	39.777ms	1	1	100.00
V2	parity	uart_smoke	1.550s	764.882us	1	1	100.00
		uart_tx_rx	16.070s	39.777ms	1	1	100.00
V2	parity_error	uart_intr	8.800s	6.314ms	1	1	100.00
		uart_rx_parity_err	22.320s	65.361ms	1	1	100.00
V2	watermark	uart_tx_rx	16.070s	39.777ms	1	1	100.00
		uart_intr	8.800s	6.314ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.562m	138.923ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	27.170s	80.852ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	20.080s	29.838ms	1	1	100.00
V2	rx_frame_err	uart_intr	8.800s	6.314ms	1	1	100.00
V2	rx_break_err	uart_intr	8.800s	6.314ms	1	1	100.00
V2	rx_timeout	uart_intr	8.800s	6.314ms	1	1	100.00
V2	perf	uart_perf	2.902m	28.522ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.360s	998.207us	1	1	100.00
V2	line_loopback	uart_loopback	1.360s	998.207us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.300s	5.808ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.990s	37.806ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.500s	1.095ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.230s	2.145ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.321m	128.394ms	1	1	100.00
V2	stress_all	uart_stress_all	2.296m	366.965ms	1	1	100.00
V2	alert_test	uart_alert_test	0.620s	23.534us	1	1	100.00
V2	intr_test	uart_intr_test	0.750s	20.016us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.410s	57.406us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.410s	57.406us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.740s	37.806us	1	1	100.00
		uart_csr_rw	0.760s	20.882us	1	1	100.00
		uart_csr_aliasing	0.860s	40.419us	1	1	100.00
		uart_same_csr_outstanding	0.900s	81.295us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.740s	37.806us	1	1	100.00
		uart_csr_rw	0.760s	20.882us	1	1	100.00
		uart_csr_aliasing	0.860s	40.419us	1	1	100.00
		uart_same_csr_outstanding	0.900s	81.295us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.000s	139.774us	1	1	100.00
		uart_tl_intg_err	1.410s	281.486us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	281.486us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.120m	45.222ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.11835409391607475710983763923189839415779640511014781453547079522987211978249
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 4476131130 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 15,                                 clk_pulses: 0
        UVM_ERROR @ 4476297797 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 4476464464 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (223 [0xdf] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 5392632963 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 27,                                 clk_pulses: 0
        UVM_ERROR @ 5392799630 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty