CHIP Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: `83a1436`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	55.539s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	55.539s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	13.689s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	21.024s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.615s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.828m	5.104ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.828m	5.104ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.828m	5.104ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.530s	10.140us	0	1	0.00
		chip_sw_example_manufacturer	2.262m		0	1	0.00
		chip_sw_example_concurrency	4.424m	3.666ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.054s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.930s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.890s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.890s		0	1	0.00
V1	xbar_smoke	xbar_smoke	21.350s	61.830us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.018m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.390m	8.707ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.480m	4.050ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	21.477s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	11.966s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	18.516s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.027s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.840s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.840s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.499m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.095m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.515m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.515m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.536m	3.507ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.006m	4.878ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.752m	14.581ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.829s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.978s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	22.737m	32.510ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.832m	4.865ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.929m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.929m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.893s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.785m	4.506ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.785m	4.506ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.651m	18.027ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.279m	4.403ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.203m	3.992ms	1	1	100.00
		chip_sw_aes_idle	3.974m	4.942ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.236m	4.116ms	1	1	100.00
		chip_sw_kmac_idle	4.579m	4.921ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.191m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.844m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.421m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.066m	12.018ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	14.020s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.649s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.597s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.037s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.229s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.212s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.839s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.020s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.649s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.597s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.037s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.229s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.212s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.839s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.001s		0	1	0.00
		chip_sw_aes_enc_jitter_en	35.260s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	45.200s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.980s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.040s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.500s		0	1	0.00
		chip_sw_clkmgr_jitter	3.374m	3.361ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.426m	5.262ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.597s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	41.490s	10.340us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	38.330s	10.260us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	39.360s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.020s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	39.100s	10.140us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.291s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.702s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.273s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.607s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.935m	13.778ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.231m	10.544ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.785m	4.506ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.997s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.231m	10.544ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	13.181s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.281s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.844s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.766s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.274s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.935m	13.778ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.752m	14.581ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.048m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.006m	9.868ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.318m	6.880ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.479m	4.879ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.935m	13.778ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	16.926s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	15.322s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.935m	13.778ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.763s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.318m	6.880ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.633s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.932s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.769s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.452s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.667s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.249s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	15.322s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.768s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.339m	5.824ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.393s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.571s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.425s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.209s		0	1	0.00
		chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.942m	9.101ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.976m	10.918ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.398s		0	1	0.00
		chip_prim_tl_access	15.415m	21.407ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.020s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.649s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.597s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.037s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.229s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.212s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.839s		0	1	0.00
		chip_rv_dm_lc_disabled	22.737m	32.510ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.772m	4.501ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	35.260s	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.510m	3.706ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.974m	4.942ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.514m	3.614ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	45.200s	10.360us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.236m	4.116ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.041m	5.433ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.886m	4.546ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	39.040s	10.280us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.942m	9.101ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	31.170s	10.320us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.395m	3.853ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.579m	4.921ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.058s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.058s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.875s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.632m	4.503ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.548s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.942m	9.101ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.980s	10.320us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.852s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	18.001s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.203m	3.992ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.203m	3.992ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.203m	3.992ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.075m	6.197ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.976m	10.918ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.976m	10.918ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.119m	9.333ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.500s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.398s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.935m	13.778ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.515m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.075m	6.197ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.942m	9.101ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.119m	9.333ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.391m	3.901ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.075m	6.197ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.942m	9.101ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.119m	9.333ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.391m	3.901ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.347s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.768s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.393s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.571s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.425s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.209s		0	1	0.00
		chip_sw_lc_ctrl_transition	17.065s		0	1	0.00
		chip_prim_tl_access	15.415m	21.407ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	15.415m	21.407ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	14.411s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.283s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.702s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.001s		0	1	0.00
		chip_sw_aes_enc_jitter_en	35.260s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	45.200s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.980s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.040s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.500s		0	1	0.00
		chip_sw_clkmgr_jitter	3.374m	3.361ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.759m	10.171ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.759m	10.171ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.986m	4.773ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.880m	4.354ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.696m	5.298ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.896m	6.335ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.243m	4.196ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.982m	5.489ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.391m	3.901ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.048m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.048m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.565m	5.434ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.528m	4.901ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.720m	5.082ms	1	1	100.00
		chip_sw_csrng_smoketest	3.391m	3.574ms	1	1	100.00
		chip_sw_gpio_smoketest	3.997m	5.012ms	1	1	100.00
		chip_sw_hmac_smoketest	4.697m	5.587ms	1	1	100.00
		chip_sw_kmac_smoketest	3.746m	4.120ms	1	1	100.00
		chip_sw_otbn_smoketest	4.748m	3.899ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.259m	3.786ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.776m	4.338ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.194m	5.657ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.538m	3.564ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.084m	3.516ms	1	1	100.00
		chip_sw_uart_smoketest	3.713m	5.581ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.498s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.054s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.018m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	14.372s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.818m	4.735ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	38.866m	60.000ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.900m	4.888ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.469m	4.497ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.670s		0	1	0.00
		chip_rv_dm_lc_disabled	22.737m	32.510ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.457s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.605s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	14.402s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.592s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.670s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.398s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.600s		0	1	0.00
		rom_volatile_raw_unlock	12.935s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.682s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	34.797s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	36.204s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.165m	4.021ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.165m	4.021ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.890s		0	1	0.00
		chip_same_csr_outstanding	7.830s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.890s		0	1	0.00
		chip_same_csr_outstanding	7.830s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	40.040s	32.197us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.910s	12.210us	1	1	100.00
		xbar_smoke_large_delays	5.109m	2.639ms	1	1	100.00
		xbar_smoke_slow_rsp	5.909m	2.186ms	1	1	100.00
		xbar_random_zero_delays	17.240s	14.387us	1	1	100.00
		xbar_random_large_delays	5.253m	2.731ms	1	1	100.00
		xbar_random_slow_rsp	14.520m	5.045ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	38.270s	64.574us	1	1	100.00
		xbar_error_and_unmapped_addr	1.699m	193.005us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.365m	213.375us	1	1	100.00
		xbar_error_and_unmapped_addr	1.699m	193.005us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.721m	866.958us	1	1	100.00
		xbar_access_same_device_slow_rsp	12.727m	4.457ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	50.550s	47.045us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	9.351m	1.314ms	1	1	100.00
		xbar_stress_all_with_error	6.130m	379.779us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	32.484m	1.085ms	1	1	100.00
		xbar_stress_all_with_reset_error	42.100s	39.240us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.061s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.738s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.598s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.243s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.710s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.484s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.331s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	13.477s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.846s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.922s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.682s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.663s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.137s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.102s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.929s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.005s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.302s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.943s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.127s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.991s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.898s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.385s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.579s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.366s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.830s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.619s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.383s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.229s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.263s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.314s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.341s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.534s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.887s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.677s		0	1	0.00
		rom_e2e_asm_init_dev	12.880s		0	1	0.00
		rom_e2e_asm_init_prod	12.179s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.478s		0	1	0.00
		rom_e2e_asm_init_rma	13.303s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.066s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.812s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.756s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.350s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.760m	5.502ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.231m	4.288ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.143s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.802s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.369s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.002s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.935m	13.778ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	13.351s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	20.783m	15.604ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.741s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.495s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.143s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.802s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.369s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.692s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.799s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.922s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.886s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.565m	15.152ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.056m	4.962ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.850m	5.481ms	1	1	100.00
		chip_plic_all_irqs_0	9.013m	6.325ms	1	1	100.00
		chip_plic_all_irqs_10	10.367m	7.400ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.593m	5.146ms	1	1	100.00
		chip_sw_dma_abort	4.272m	4.134ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.044s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.791s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.170s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.689s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.145s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.347s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.255s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.291s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.369s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.856s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.091m	3.431ms	1	1	100.00
		chip_sw_mbx_smoketest	4.820m	4.063ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.51896937252223377621524395108675608815966823169437394143534886240314055082350
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 123.127s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.93003747773119943794776854369677963047549957517286802581985517070831219378749
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 79.964s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.104346842779868999823164459620113475618721894242320559015724619747172138906655
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Target //sw/device/tests:sleep_pin_wake_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 79.331s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.24245417096892993640071140773766101183800691242308962804066182127846581777315
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 51.229s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.65492129319994226231318588687762636234675498639835582825645347484513994558574
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 44.162s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.13738903625824138322992632297986082550193881022199866557472753563947337081268
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.88777815282148922100315174489933809710706453167584796371576056408595398127945
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.13658444433708741887564452272510233176870598181988216895508665876671018350424
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.41260983964563173384946048267683543276001902862787090867617730026063613365791
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.108563711520210490300137635309483330814678115662672894117404138851205316703979
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.114412034368964849239028811500477792833624319958457502130512992374780424338258
Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.567325 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.567325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.66727975230532362371393507182217497821483761954509025226673640401488588561294
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.715693 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.715693 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.78351855349787517404128798168038103247890139079255047153848732272075480717177
Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.974210 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.974210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.226097516954707753405062234723566987556781573718235350401362572730199263672
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.465609 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.465609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.98915521186830419390228296988115646649313608630567772644050497676302430019568
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.14564853155183290995979045852626671268593635542486469196313721657000723518558
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.64647502603602619263819047284889128992177027321248847542966194285452402449274
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.35431158475550434033934066618594662727142867637129523501396649639373387952579
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.470784 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.470784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.24255646577777470287910567163632929840287500282191695268262015366415046377905
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.577986 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.577986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.41467178951115704596477874910766071651598932340494686544581460490463551917913
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.435405 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.435405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.62982229412583625017954495839085334498211115902678995944761677360193188838144
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9100.535680 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3619320588694067470302394060051019636280707253757154215783468730492303692075707025502835532200260673347760439922944160754428009651999656605530023681940572 [0x451adedaaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3c34c6e2b7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 9100.535680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.19583118577627199181793593012042326178747950089637680882071187976438205854445
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5824.493010 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12465499182060721176494023384727566684554792324074848486671283598992311460738073435295214723115050063603338637954072038540179417431694073869988792235285596 [0xee02173daae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd36854a7cc7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 5824.493010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.97160145896577314451946640970624916179372343240560680071113282695743031814925
Line 6260, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3506.510309 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: 'h30480000  a_data: 'hd66e6915  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h1  a_user: 'h24891  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3506.510309 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.94156376274378888356642865347312089681087960876929938189791446487435942925188
Line 6260, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4877.656313 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: 'h30480000  a_data: 'hf4e05869  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h0  a_user: 'h26944  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4877.656313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.7377007848631094027555703521873389062175582324297519338395975747169472814735
    Line 604, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1101381059058687234593460449302491627617702824505944909573424632126335802727
    Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4050.163960 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4050.163960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_raw_to_scrap.2019658515429908512055614740681634650946536006756047756581418584588115996923
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.50214103303821801485363519520941696298266556533605186917032895644455175018361
    Line 625, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6880.223746 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6880.223746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.7140387559906515636286139143956878551787825218282500868720809899025098989256
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4772.569084 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4772.569084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.20518261990488002817051047034366419512440161292533980143407707828499040478352
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4354.465534 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4354.465534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.84431378637526724271951636046360495526035247282425254172550911449754172021884
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4506.159487 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4506.159487 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.101160585939341864752924999432802940239363332750957214458274755056139453136662
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6335.182400 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6335.182400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.45873184892070178745273615364538354919740586063885898018542833646263152453180
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.139462157565484619232586465632406716696702807541869704968447642489412390555
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4020.542513 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4020.542513 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.71331986998984569712604986769526051840337052189065020693742565564318620380976
    Line 373, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14580.603676 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14580.603676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.12607298731573503050974435155786947479930345392254932265617729977896416707547
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.53460592889583553196733241802959456803090938989324648065704299429074040143268
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4134.276444 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4134.276444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```