DMA Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	6.000s	587.728us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	260.099us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	1.100ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	13.419us	1	1	100.00
V1	csr_rw	dma_csr_rw	3.000s	26.102us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	13.000s	16.058ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	895.851us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	3.000s	25.918us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	3.000s	26.102us	1	1	100.00
		dma_csr_aliasing	8.000s	895.851us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	30.000s	6.596ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	4.050m	36.242ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	2.050m	21.801ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	2.050m	21.801ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	4.050m	36.242ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.617m	14.307ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	2.050m	21.801ms	1	1	100.00
V2	dma_abort	dma_abort	11.000s	1.480ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.183m	74.730ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	15.793us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	13.100us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	163.925us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	163.925us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	13.419us	1	1	100.00
		dma_csr_rw	3.000s	26.102us	1	1	100.00
		dma_csr_aliasing	8.000s	895.851us	1	1	100.00
		dma_same_csr_outstanding	3.000s	41.095us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	13.419us	1	1	100.00
		dma_csr_rw	3.000s	26.102us	1	1	100.00
		dma_csr_aliasing	8.000s	895.851us	1	1	100.00
		dma_same_csr_outstanding	3.000s	41.095us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	17.000s	4.565ms	1	1	100.00
		dma_generic_stress	2.617m	14.307ms	1	1	100.00
		dma_handshake_stress	2.050m	21.801ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	10.000s	1.269ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	326.484us	1	1	100.00
		dma_sec_cm	2.000s	11.298us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.633m	172.461ms	1	1	100.00
		dma_longer_transfer	5.000s	125.818us	1	1	100.00
		dma_stress_all_with_rand_reset	8.000s	1.282ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:946) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.62998515556033366481251799494520452071625110944497999309555311733191991910771
      Line 98, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1282227084ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1282227084ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---