EDN Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.920s 29.985us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.770s 15.111us 1 1 100.00
V1 csr_rw edn_csr_rw 0.860s 57.415us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.440s 133.070us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.170s 50.552us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.860s 56.870us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.860s 57.415us 1 1 100.00
edn_csr_aliasing 1.170s 50.552us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.030s 25.408us 1 1 100.00
V2 csrng_commands edn_genbits 1.030s 25.408us 1 1 100.00
V2 genbits edn_genbits 1.030s 25.408us 1 1 100.00
V2 interrupts edn_intr 0.820s 32.683us 1 1 100.00
V2 alerts edn_alert 0.960s 83.967us 1 1 100.00
V2 errs edn_err 0.830s 44.752us 1 1 100.00
V2 disable edn_disable 0.740s 17.874us 1 1 100.00
edn_disable_auto_req_mode 1.010s 105.855us 1 1 100.00
V2 stress_all edn_stress_all 2.970s 1.160ms 1 1 100.00
V2 intr_test edn_intr_test 0.760s 50.471us 1 1 100.00
V2 alert_test edn_alert_test 0.750s 92.864us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.340s 48.103us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.340s 48.103us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.770s 15.111us 1 1 100.00
edn_csr_rw 0.860s 57.415us 1 1 100.00
edn_csr_aliasing 1.170s 50.552us 1 1 100.00
edn_same_csr_outstanding 1.130s 68.731us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.770s 15.111us 1 1 100.00
edn_csr_rw 0.860s 57.415us 1 1 100.00
edn_csr_aliasing 1.170s 50.552us 1 1 100.00
edn_same_csr_outstanding 1.130s 68.731us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.200s 322.414us 1 1 100.00
edn_tl_intg_err 1.330s 54.600us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.940s 20.055us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 0.960s 83.967us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.200s 322.414us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.200s 322.414us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.200s 322.414us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.200s 322.414us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0.960s 83.967us 1 1 100.00
edn_sec_cm 4.200s 322.414us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0.960s 83.967us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.330s 54.600us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets