HMAC Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.470s 522.216us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.750s 47.006us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.710s 29.344us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.170s 2.184ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.990s 2.283ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.650s 98.193us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.710s 29.344us 1 1 100.00
hmac_csr_aliasing 5.990s 2.283ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 5.030s 1.681ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.191m 3.718ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.079m 11.046ms 1 1 100.00
hmac_test_sha384_vectors 17.890s 885.380us 1 1 100.00
hmac_test_sha512_vectors 6.164m 47.288ms 1 1 100.00
hmac_test_hmac256_vectors 8.750s 387.977us 1 1 100.00
hmac_test_hmac384_vectors 10.350s 369.989us 1 1 100.00
hmac_test_hmac512_vectors 9.460s 1.864ms 1 1 100.00
V2 burst_wr hmac_burst_wr 20.560s 2.402ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.661m 14.200ms 1 1 100.00
V2 error hmac_error 38.420s 1.582ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 47.410s 1.423ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.470s 522.216us 1 1 100.00
hmac_long_msg 5.030s 1.681ms 1 1 100.00
hmac_back_pressure 1.191m 3.718ms 1 1 100.00
hmac_datapath_stress 1.661m 14.200ms 1 1 100.00
hmac_burst_wr 20.560s 2.402ms 1 1 100.00
hmac_stress_all 12.676m 28.433ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.470s 522.216us 1 1 100.00
hmac_long_msg 5.030s 1.681ms 1 1 100.00
hmac_back_pressure 1.191m 3.718ms 1 1 100.00
hmac_datapath_stress 1.661m 14.200ms 1 1 100.00
hmac_wipe_secret 47.410s 1.423ms 1 1 100.00
hmac_test_sha256_vectors 3.079m 11.046ms 1 1 100.00
hmac_test_sha384_vectors 17.890s 885.380us 1 1 100.00
hmac_test_sha512_vectors 6.164m 47.288ms 1 1 100.00
hmac_test_hmac256_vectors 8.750s 387.977us 1 1 100.00
hmac_test_hmac384_vectors 10.350s 369.989us 1 1 100.00
hmac_test_hmac512_vectors 9.460s 1.864ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.470s 522.216us 1 1 100.00
hmac_long_msg 5.030s 1.681ms 1 1 100.00
hmac_back_pressure 1.191m 3.718ms 1 1 100.00
hmac_datapath_stress 1.661m 14.200ms 1 1 100.00
hmac_burst_wr 20.560s 2.402ms 1 1 100.00
hmac_error 38.420s 1.582ms 1 1 100.00
hmac_wipe_secret 47.410s 1.423ms 1 1 100.00
hmac_test_sha256_vectors 3.079m 11.046ms 1 1 100.00
hmac_test_sha384_vectors 17.890s 885.380us 1 1 100.00
hmac_test_sha512_vectors 6.164m 47.288ms 1 1 100.00
hmac_test_hmac256_vectors 8.750s 387.977us 1 1 100.00
hmac_test_hmac384_vectors 10.350s 369.989us 1 1 100.00
hmac_test_hmac512_vectors 9.460s 1.864ms 1 1 100.00
hmac_stress_all 12.676m 28.433ms 1 1 100.00
V2 stress_all hmac_stress_all 12.676m 28.433ms 1 1 100.00
V2 alert_test hmac_alert_test 0.520s 15.099us 1 1 100.00
V2 intr_test hmac_intr_test 0.630s 14.318us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.130s 103.202us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.130s 103.202us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.750s 47.006us 1 1 100.00
hmac_csr_rw 0.710s 29.344us 1 1 100.00
hmac_csr_aliasing 5.990s 2.283ms 1 1 100.00
hmac_same_csr_outstanding 1.230s 62.014us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.750s 47.006us 1 1 100.00
hmac_csr_rw 0.710s 29.344us 1 1 100.00
hmac_csr_aliasing 5.990s 2.283ms 1 1 100.00
hmac_same_csr_outstanding 1.230s 62.014us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.860s 496.798us 1 1 100.00
hmac_tl_intg_err 2.150s 605.555us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.150s 605.555us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.470s 522.216us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.640s 356.963us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.740m 5.321ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.720s 30.233us 1 1 100.00
TOTAL 28 28 100.00