I2C Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	17.260s	29.348ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	15.280s	1.077ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.880s	40.986us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.890s	22.909us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.830s	697.532us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.000s	98.373us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.890s	506.133us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.890s	22.909us	1	1	100.00
		i2c_csr_aliasing	1.000s	98.373us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.000s	76.251us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	3.883m	84.192ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.530m	51.020ms	1	1	100.00
V2	host_override	i2c_host_override	0.870s	15.656us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	56.030s	24.365ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	56.430s	7.740ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.420s	144.059us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.390s	597.191us	1	1	100.00
		i2c_host_fifo_reset_rx	3.090s	166.172us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	55.870s	24.139ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.250s	3.244ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.130s	82.250us	1	1	100.00
V2	target_glitch	i2c_target_glitch	3.730s	2.365ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	3.321m	16.801ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.260s	819.265us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	4.780s	357.903us	1	1	100.00
		i2c_target_intr_smoke	5.520s	931.687us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.470s	488.801us	1	1	100.00
		i2c_target_fifo_reset_tx	1.320s	179.214us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.990s	16.628ms	1	1	100.00
		i2c_target_stress_rd	4.780s	357.903us	1	1	100.00
		i2c_target_intr_stress_wr	38.670s	15.280ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.940s	1.479ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	12.920s	938.215us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.200s	2.159ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.600s	1.067ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.050s	568.649us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.420s	337.412us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.530m	51.020ms	1	1	100.00
		i2c_host_perf_precise	51.810s	5.788ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.250s	3.244ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	9.630s	1.133ms	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.330s	3.356ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.050s	2.215ms	1	1	100.00
		i2c_target_nack_txstretch	1.260s	158.131us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.860s	433.991us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.750s	2.534ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.620s	69.783us	1	1	100.00
V2	intr_test	i2c_intr_test	0.910s	38.692us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.740s	384.284us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.740s	384.284us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.880s	40.986us	1	1	100.00
		i2c_csr_rw	0.890s	22.909us	1	1	100.00
		i2c_csr_aliasing	1.000s	98.373us	1	1	100.00
		i2c_same_csr_outstanding	1.170s	55.646us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.880s	40.986us	1	1	100.00
		i2c_csr_rw	0.890s	22.909us	1	1	100.00
		i2c_csr_aliasing	1.000s	98.373us	1	1	100.00
		i2c_same_csr_outstanding	1.170s	55.646us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.160s	54.470us	1	1	100.00
		i2c_sec_cm	0.920s	308.607us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.160s	54.470us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.700s	643.200us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.360s	335.626us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.590s	3.721ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.106901332303897577268620431017664310695968633490160161120261392811719022157902
      Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 643200224 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 643200224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.30225380916662770077917688226930512583513270214843796772052776656339893447726
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3721250178 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3721250178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.48328142546240177468822761380484500765870148545844298686357102784829366911367
      Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  76250875 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  76250875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.53318451354570910171296394230080816217798790841098304516256792480253673201266
      Line 129, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 84191976464 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @3840045
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.20234873811366141629282820202246453583346426936065036980175285362316484801225
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2365140584 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2365140584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.70641689216045585420636453545301701960955229451239290638364381622520329842211
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 335626079 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 18 [0x12])
        UVM_INFO @ 335626079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.68745363311955451626064993942075818052489968722874482608448665867584638773771
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 158130979 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 158130979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---