KMAC/MASKED Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	16.230s	5.091ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.910s	27.758us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.950s	48.349us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.600s	3.469ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.810s	839.608us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.270s	40.612us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.950s	48.349us	1	1	100.00
		kmac_csr_aliasing	3.810s	839.608us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.730s	22.941us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.250s	46.530us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	26.667m	73.647ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.637m	13.025ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.043m	269.387ms	1	1	100.00
		kmac_test_vectors_sha3_256	33.370s	2.530ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.210s	3.699ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.997m	32.376ms	1	1	100.00
		kmac_test_vectors_shake_128	3.067m	18.153ms	1	1	100.00
		kmac_test_vectors_shake_256	5.031m	48.600ms	1	1	100.00
		kmac_test_vectors_kmac	2.880s	262.461us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.730s	155.418us	1	1	100.00
V2	sideload	kmac_sideload	2.457m	24.903ms	1	1	100.00
V2	app	kmac_app	1.385m	2.050ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.138m	34.436ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	38.840s	4.349ms	1	1	100.00
V2	error	kmac_error	4.340m	200.000ms	0	1	0.00
V2	key_error	kmac_key_error	3.400s	1.395ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.110s	823.371us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.020s	16.930us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.000s	36.179us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	23.170s	6.006ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.490s	37.090us	1	1	100.00
V2	stress_all	kmac_stress_all	20.801m	210.764ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.880s	15.875us	1	1	100.00
V2	alert_test	kmac_alert_test	1.050s	13.820us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.630s	125.934us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.630s	125.934us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.910s	27.758us	1	1	100.00
		kmac_csr_rw	0.950s	48.349us	1	1	100.00
		kmac_csr_aliasing	3.810s	839.608us	1	1	100.00
		kmac_same_csr_outstanding	1.440s	64.353us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.910s	27.758us	1	1	100.00
		kmac_csr_rw	0.950s	48.349us	1	1	100.00
		kmac_csr_aliasing	3.810s	839.608us	1	1	100.00
		kmac_same_csr_outstanding	1.440s	64.353us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.860s	100.424us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.860s	100.424us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.860s	100.424us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.860s	100.424us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.630s	1.080ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.026m	24.293ms	1	1	100.00
		kmac_tl_intg_err	2.260s	200.813us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.260s	200.813us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.490s	37.090us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	16.230s	5.091ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.457m	24.903ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.860s	100.424us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.026m	24.293ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.026m	24.293ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.026m	24.293ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	16.230s	5.091ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.490s	37.090us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.026m	24.293ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.681m	9.128ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	16.230s	5.091ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	28.240s	2.556ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test kmac_error has 1 failures.

    • 0.kmac_error.100634738955370928355322510857790578034882379472713162345047578220584690553449
      Line 209, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---