| V1 |
smoke |
kmac_smoke |
18.180s |
1.247ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.810s |
47.439us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
0.980s |
35.425us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
6.610s |
764.799us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
6.220s |
388.951us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.690s |
69.087us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
0.980s |
35.425us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.220s |
388.951us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.820s |
10.330us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.160s |
48.121us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
35.624m |
459.548ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
6.942m |
60.333ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
34.100s |
5.441ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
30.710s |
2.384ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
15.160s |
425.198us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
10.920s |
775.279us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.640m |
57.659ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
1.468m |
5.018ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.120s |
453.546us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
1.740s |
163.528us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
2.472m |
122.821ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
1.864m |
11.681ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
46.090s |
1.562ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
42.880s |
2.844ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
1.641m |
5.341ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
5.170s |
2.358ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
0.990s |
20.260us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
21.130s |
2.582ms |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
7.620s |
150.887us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
34.160s |
5.567ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.220s |
118.323us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
10.710m |
145.102ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.720s |
44.472us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.740s |
50.071us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
3.100s |
2.155ms |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
3.100s |
2.155ms |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.810s |
47.439us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.980s |
35.425us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.220s |
388.951us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.470s |
59.906us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.810s |
47.439us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.980s |
35.425us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.220s |
388.951us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.470s |
59.906us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.590s |
84.330us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.590s |
84.330us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.590s |
84.330us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.590s |
84.330us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
3.340s |
892.176us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
43.730s |
18.720ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.110s |
214.683us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.110s |
214.683us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.220s |
118.323us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
18.180s |
1.247ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
2.472m |
122.821ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.590s |
84.330us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
43.730s |
18.720ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
43.730s |
18.720ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
43.730s |
18.720ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
18.180s |
1.247ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.220s |
118.323us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
43.730s |
18.720ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
2.436m |
10.117ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
18.180s |
1.247ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
44.170s |
11.425ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |