975e648| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 48.000s | 11.790ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 5.000s | 34.900us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 55.104us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 131.324us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 3.000s | 115.828us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 26.777us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 55.104us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 3.000s | 115.828us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 12.000s | 1.714ms | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 13.000s | 995.784us | 0 | 1 | 0.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 35.000s | 6.529ms | 1 | 1 | 100.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 14.000s | 2.462ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 6.000s | 20.112us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 5.000s | 45.175us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 6.000s | 77.590us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 6.000s | 77.590us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 5.000s | 34.900us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 55.104us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 115.828us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 23.548us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 5.000s | 34.900us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 55.104us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 115.828us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 23.548us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 6 | 8 | 75.00 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 5.000s | 124.537us | 1 | 1 | 100.00 |
| mbx_sec_cm | 7.000s | 18.372us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 14 | 16 | 87.50 |
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:
0.mbx_stress.95870017346335375619328252469384359224234932682515407748780017150090933437824
Line 264, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_ERROR @ 1713663939 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (1887509056 [0x70811a40] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 1713663939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:
0.mbx_stress_zero_delays.86900914806930320075008087682033191203474195535517530138947445884859614779128
Line 644, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log
UVM_ERROR @ 995784461 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 995784461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---