ROM_CTRL/32KB Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.250s 175.053us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.830s 1.193ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.690s 184.094us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 3.570s 558.416us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.760s 868.835us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.670s 1.095ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.690s 184.094us 1 1 100.00
rom_ctrl_csr_aliasing 4.760s 868.835us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.330s 125.285us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.540s 603.359us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.720s 181.446us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 15.170s 2.194ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.290s 475.522us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.820s 164.470us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.380s 171.631us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.380s 171.631us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.830s 1.193ms 1 1 100.00
rom_ctrl_csr_rw 4.690s 184.094us 1 1 100.00
rom_ctrl_csr_aliasing 4.760s 868.835us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.710s 185.190us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.830s 1.193ms 1 1 100.00
rom_ctrl_csr_rw 4.690s 184.094us 1 1 100.00
rom_ctrl_csr_aliasing 4.760s 868.835us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.710s 185.190us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 13.400s 1.081ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.714m 425.083us 1 1 100.00
rom_ctrl_tl_intg_err 42.420s 307.994us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.714m 425.083us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.714m 425.083us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.714m 425.083us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.714m 425.083us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.250s 175.053us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.250s 175.053us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.250s 175.053us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 42.420s 307.994us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.290s 475.522us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.424m 12.067ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 13.400s 1.081ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.714m 425.083us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.220m 18.967ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00