RV_TIMER Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.740s	17.683us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.830s	18.797us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.710s	15.860us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.680s	560.007us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	150.829us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.920s	95.143us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.710s	15.860us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	150.829us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.730s	37.049us	1	1	100.00
V2	disabled	rv_timer_disabled	1.190s	726.416us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	56.140s	47.840ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	56.140s	47.840ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.590s	4.004ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.810s	13.944us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.770s	194.624us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.860s	159.216us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.860s	159.216us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.830s	18.797us	1	1	100.00
		rv_timer_csr_rw	0.710s	15.860us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	150.829us	1	1	100.00
		rv_timer_same_csr_outstanding	1.000s	138.675us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.830s	18.797us	1	1	100.00
		rv_timer_csr_rw	0.710s	15.860us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	150.829us	1	1	100.00
		rv_timer_same_csr_outstanding	1.000s	138.675us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.100s	378.616us	1	1	100.00
		rv_timer_tl_intg_err	1.160s	224.739us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.160s	224.739us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.680s	32.230us	1	1	100.00
V3	max_value	rv_timer_max	0.660s	51.191us	1	1	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	40.690s	5.952ms	1	1	100.00
V3		TOTAL			3	3	100.00
		TOTAL			19	19	100.00