SPI_DEVICE/1R1W Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.455m	17.267ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.150s	42.513us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.910s	150.832us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.690s	545.257us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.310s	412.214us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.950s	196.116us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.910s	150.832us	1	1	100.00
		spi_device_csr_aliasing	10.310s	412.214us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.640s	14.260us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.050s	239.394us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.820s	35.014us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.670s	4.375us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.830s	3.553us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.060s	47.752us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.060s	47.752us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.890s	640.552us	1	1	100.00
		spi_device_tpm_sts_read	0.860s	51.373us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	0.700s	14.408us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.620s	1.176ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.000s	9.839ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.000s	9.839ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	11.450s	3.197ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	11.450s	3.197ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	11.450s	3.197ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	11.450s	3.197ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	11.450s	3.197ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	14.410s	32.059ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	19.070s	3.785ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	19.070s	3.785ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	19.070s	3.785ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.760s	298.896us	1	1	100.00
		spi_device_read_buffer_direct	3.270s	132.070us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	19.070s	3.785ms	1	1	100.00
		spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	16.570s	5.030ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.870s	4.098ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.870s	4.098ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.455m	17.267ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.284m	30.085ms	1	1	100.00
V2	stress_all	spi_device_stress_all	5.252m	212.345ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.930s	12.840us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.820s	62.218us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.870s	62.985us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.870s	62.985us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.150s	42.513us	1	1	100.00
		spi_device_csr_rw	1.910s	150.832us	1	1	100.00
		spi_device_csr_aliasing	10.310s	412.214us	1	1	100.00
		spi_device_same_csr_outstanding	3.070s	716.063us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.150s	42.513us	1	1	100.00
		spi_device_csr_rw	1.910s	150.832us	1	1	100.00
		spi_device_csr_aliasing	10.310s	412.214us	1	1	100.00
		spi_device_same_csr_outstanding	3.070s	716.063us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	0.880s	248.515us	1	1	100.00
		spi_device_tl_intg_err	6.960s	417.211us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.960s	417.211us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	31.670s	2.508ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.9664921595635919869735442089203983303633895383349724534018574639541947372890
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3135393 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[97])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3135393 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3135393 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.28436361838548316474768777792170310844782440555091267097148603647534613167372
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1066639 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6f801b [11011111000000000011011] vs 0x0 [0])
        UVM_ERROR @   1074639 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7f051d [11111110000010100011101] vs 0x0 [0])
        UVM_ERROR @   1172639 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xefd1d7 [111011111101000111010111] vs 0x0 [0])
        UVM_ERROR @   1245639 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa5ee12 [101001011110111000010010] vs 0x0 [0])
        UVM_ERROR @   1313639 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc9811a [110010011000000100011010] vs 0x0 [0])