SPI_HOST Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.000s	1.318ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	55.086us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	21.542us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	233.188us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	16.086us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	255.175us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	21.542us	1	1	100.00
		spi_host_csr_aliasing	3.000s	16.086us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	16.334us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	25.869us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	24.044us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	58.904us	1	1	100.00
		spi_host_error_cmd	3.000s	19.891us	1	1	100.00
		spi_host_event	12.000s	864.382us	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	750.967us	1	1	100.00
V2	speed	spi_host_speed	7.000s	750.967us	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	750.967us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	33.262us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	27.305us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	750.967us	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	750.967us	1	1	100.00
V2	duplex	spi_host_smoke	11.000s	1.318ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	11.000s	1.318ms	1	1	100.00
V2	stress_all	spi_host_stress_all	8.000s	1.492ms	1	1	100.00
V2	spien	spi_host_spien	6.000s	2.533ms	1	1	100.00
V2	stall	spi_host_status_stall	1.300m	4.470ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	7.000s	3.588ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	58.904us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	41.779us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	41.025us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	95.976us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	95.976us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	55.086us	1	1	100.00
		spi_host_csr_rw	3.000s	21.542us	1	1	100.00
		spi_host_csr_aliasing	3.000s	16.086us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	21.800us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	55.086us	1	1	100.00
		spi_host_csr_rw	3.000s	21.542us	1	1	100.00
		spi_host_csr_aliasing	3.000s	16.086us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	21.800us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	212.385us	1	1	100.00
		spi_host_sec_cm	2.000s	249.447us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	212.385us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.567m	6.645ms	1	1	100.00
		TOTAL			26	26	100.00