SRAM_CTRL/MAIN Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.230s	2.638ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.630s	41.155us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.610s	35.190us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.270s	121.487us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	68.670us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.230s	691.125us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.610s	35.190us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	68.670us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.379m	20.916ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	55.850s	2.795ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.261m	29.397ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.675m	16.464ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	13.922m	70.614ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.980m	73.608ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	27.090s	18.611ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.801m	35.500ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.160s	7.883ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.730m	14.452ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	18.040s	8.886ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	9.390s	712.641us	1	1	100.00
		sram_ctrl_throughput_w_readback	16.520s	2.726ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.343m	10.567ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.470s	362.090us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	45.393m	122.629ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.840s	44.882us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.860s	31.408us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.860s	31.408us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.630s	41.155us	1	1	100.00
		sram_ctrl_csr_rw	0.610s	35.190us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	68.670us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.820s	25.871us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.630s	41.155us	1	1	100.00
		sram_ctrl_csr_rw	0.610s	35.190us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	68.670us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.820s	25.871us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.430s	13.734ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.840s	6.862us	0	1	0.00
		sram_ctrl_tl_intg_err	2.090s	304.061us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.840s	6.862us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.090s	304.061us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.343m	10.567ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.343m	10.567ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.610s	35.190us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.801m	35.500ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.801m	35.500ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.801m	35.500ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	27.090s	18.611ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.030s	680.210us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.430s	13.734ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.840s	2.647ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.230s	2.638ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.230s	2.638ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.801m	35.500ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.840s	6.862us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	27.090s	18.611ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.840s	6.862us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.840s	6.862us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.230s	2.638ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.840s	6.862us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.410s	920.994us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.48303491750744503805744639072351299720780508454016260646844017720440683567397
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 680209844 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 680209844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.70172653925723198371224698365667816110994527567139636794268199120412597571342
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6862201 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6862201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---