UART Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: 975e648

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	4.410s	6.353ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	46.064us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.810s	14.335us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.240s	92.868us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.680s	16.548us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.750s	16.282us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.810s	14.335us	1	1	100.00
		uart_csr_aliasing	0.680s	16.548us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	18.310s	35.154ms	1	1	100.00
V2	parity	uart_smoke	4.410s	6.353ms	1	1	100.00
		uart_tx_rx	18.310s	35.154ms	1	1	100.00
V2	parity_error	uart_intr	3.672m	197.080ms	1	1	100.00
		uart_rx_parity_err	2.851m	265.854ms	1	1	100.00
V2	watermark	uart_tx_rx	18.310s	35.154ms	1	1	100.00
		uart_intr	3.672m	197.080ms	1	1	100.00
V2	fifo_full	uart_fifo_full	35.080s	34.154ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	39.130s	72.860ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	9.950s	16.991ms	1	1	100.00
V2	rx_frame_err	uart_intr	3.672m	197.080ms	1	1	100.00
V2	rx_break_err	uart_intr	3.672m	197.080ms	1	1	100.00
V2	rx_timeout	uart_intr	3.672m	197.080ms	1	1	100.00
V2	perf	uart_perf	11.063m	19.010ms	1	1	100.00
V2	sys_loopback	uart_loopback	13.080s	5.609ms	1	1	100.00
V2	line_loopback	uart_loopback	13.080s	5.609ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	16.480s	54.776ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.180s	48.930ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.770s	1.084ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.900s	1.791ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.660m	166.927ms	1	1	100.00
V2	stress_all	uart_stress_all	7.876m	172.616ms	1	1	100.00
V2	alert_test	uart_alert_test	0.810s	26.738us	1	1	100.00
V2	intr_test	uart_intr_test	0.760s	12.968us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	0.890s	37.770us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	0.890s	37.770us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	46.064us	1	1	100.00
		uart_csr_rw	0.810s	14.335us	1	1	100.00
		uart_csr_aliasing	0.680s	16.548us	1	1	100.00
		uart_same_csr_outstanding	0.720s	73.235us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	46.064us	1	1	100.00
		uart_csr_rw	0.810s	14.335us	1	1	100.00
		uart_csr_aliasing	0.680s	16.548us	1	1	100.00
		uart_same_csr_outstanding	0.720s	73.235us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.200s	73.306us	1	1	100.00
		uart_tl_intg_err	1.710s	111.087us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.710s	111.087us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	6.090s	2.351ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.42726254416283562044275389532039024706752991844688485188431262280898761068363
      Line 77, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 53679114611 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @ 53679154611 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 53679194611 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (213 [0xd5] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 53679234611 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 53679274611 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (213 [0xd5] vs 247 [0xf7]) reg name: uart_reg_block.rdata