CHIP Simulation Results

Thursday September 11 2025 16:03:02 UTC

GitHub Revision: `975e648`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.889m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.889m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.484m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.668m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.313m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.118m	5.406ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.118m	5.406ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.118m	5.406ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.000s	10.160us	0	1	0.00
		chip_sw_example_manufacturer	2.936m		0	1	0.00
		chip_sw_example_concurrency	4.856m	5.281ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.741s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.290s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.330s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.330s		0	1	0.00
V1	xbar_smoke	xbar_smoke	21.140s	59.483us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.962m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.572m	8.771ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.837m	5.309ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	57.457s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	28.874s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	48.528s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	30.582s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.810s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.810s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.440m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.955m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.142m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.142m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.512m	5.098ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.789m	5.448ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.440m	14.715ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.543s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.064s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	11.682m	23.897ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.499m	6.287ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.949m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.949m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	15.835s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.368m	4.282ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.368m	4.282ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.493m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.163m	5.159ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.805m	4.640ms	1	1	100.00
		chip_sw_aes_idle	5.356m	5.679ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.927m	3.759ms	1	1	100.00
		chip_sw_kmac_idle	4.024m	3.723ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.276m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.256m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.094m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.732m	12.019ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	15.468s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.588s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.188s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.615s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.406s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.430s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.609s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.468s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.588s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.188s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.615s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.406s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.430s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.609s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.556s		0	1	0.00
		chip_sw_aes_enc_jitter_en	40.630s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.760s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.700s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	38.260s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.202s		0	1	0.00
		chip_sw_clkmgr_jitter	3.473m	4.506ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.325m	5.738ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.558s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	38.160s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	36.850s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	40.050s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	36.530s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.440s	10.220us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.812s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.663s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	15.127s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.539s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.290m	13.106ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.635m	13.704ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.368m	4.282ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.538s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.635m	13.704ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.722s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	20.299s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	16.215s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.016s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.669s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.290m	13.106ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.440m	14.715ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	22.628m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.139m	7.534ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.366m	9.856ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.855m	3.698ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.290m	13.106ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.925s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.117s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.290m	13.106ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.693s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.366m	9.856ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.605s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.630s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.502s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.343s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.706s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.496s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.117s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	12.296s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.447m	8.387ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.276s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.104s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	27.759s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	23.714s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.769m	5.724ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	12.012m	10.606ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	15.145s		0	1	0.00
		chip_prim_tl_access	11.844m	21.379ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.468s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.588s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.188s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.615s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.406s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.430s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.609s		0	1	0.00
		chip_rv_dm_lc_disabled	11.682m	23.897ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.458m	5.227ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	40.630s	10.320us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.083m	5.407ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.356m	5.679ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.359m	5.334ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	37.760s	10.140us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.927m	3.759ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.622m	4.132ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.063m	3.695ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	38.260s	10.160us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.769m	5.724ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	31.120s	10.140us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.022m	5.528ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.024m	3.723ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.732s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.732s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.687s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.147m	5.920ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	16.396s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.769m	5.724ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.700s	10.200us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	16.113s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.556s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.805m	4.640ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.805m	4.640ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.805m	4.640ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.776m	6.056ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.012m	10.606ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.012m	10.606ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.921m	10.309ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.202s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	15.145s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.290m	13.106ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.142m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.776m	6.056ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.769m	5.724ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.921m	10.309ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.067m	4.929ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.776m	6.056ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.769m	5.724ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.921m	10.309ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.067m	4.929ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.036s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	12.296s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.276s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.104s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	27.759s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	23.714s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.485s		0	1	0.00
		chip_prim_tl_access	11.844m	21.379ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	11.844m	21.379ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	18.745s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.880s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.663s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.556s		0	1	0.00
		chip_sw_aes_enc_jitter_en	40.630s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.760s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.700s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	38.260s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.202s		0	1	0.00
		chip_sw_clkmgr_jitter	3.473m	4.506ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.543m	7.492ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.543m	7.492ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.791m	5.705ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.379m	4.650ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.889m	5.351ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.123m	6.342ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.391m	4.789ms	0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.256m	4.152ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.067m	4.929ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	22.628m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	22.628m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.984m	5.049ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.802m	5.640ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.582m	4.118ms	1	1	100.00
		chip_sw_csrng_smoketest	4.152m	4.951ms	1	1	100.00
		chip_sw_gpio_smoketest	4.166m	5.958ms	1	1	100.00
		chip_sw_hmac_smoketest	4.143m	3.872ms	1	1	100.00
		chip_sw_kmac_smoketest	4.431m	4.456ms	1	1	100.00
		chip_sw_otbn_smoketest	4.390m	5.254ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.961m	3.685ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.392m	4.065ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.867m	4.549ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.474m	5.626ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.162m	3.712ms	1	1	100.00
		chip_sw_uart_smoketest	3.524m	5.168ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.191s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.741s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.962m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.599s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.368m	5.928ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.868m	5.310ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	43.077m	60.000ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	4.788m	6.418ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.518s		0	1	0.00
		chip_rv_dm_lc_disabled	11.682m	23.897ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	24.772s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.483s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.985s		0	1	0.00
		chip_sw_lc_walkthrough_rma	29.173s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.518s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	17.510s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.597s		0	1	0.00
		rom_volatile_raw_unlock	11.915s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	13.217s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.751m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.813m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.780m	3.188ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.780m	3.188ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.330s		0	1	0.00
		chip_same_csr_outstanding	13.900s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.330s		0	1	0.00
		chip_same_csr_outstanding	13.900s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.953m	351.889us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.150s	12.922us	1	1	100.00
		xbar_smoke_large_delays	3.842m	2.054ms	1	1	100.00
		xbar_smoke_slow_rsp	4.825m	1.851ms	1	1	100.00
		xbar_random_zero_delays	22.790s	23.113us	1	1	100.00
		xbar_random_large_delays	22.927m	11.841ms	1	1	100.00
		xbar_random_slow_rsp	3.420m	1.271ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	37.680s	27.171us	1	1	100.00
		xbar_error_and_unmapped_addr	43.680s	75.928us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	28.790s	34.008us	1	1	100.00
		xbar_error_and_unmapped_addr	43.680s	75.928us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.625m	783.582us	1	1	100.00
		xbar_access_same_device_slow_rsp	24.700m	8.719ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	15.670s	37.831us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	15.364m	2.233ms	1	1	100.00
		xbar_stress_all_with_error	9.959m	1.706ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	14.753m	414.050us	1	1	100.00
		xbar_stress_all_with_reset_error	19.703m	922.720us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.700s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.796s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.062s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	15.048s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.217s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.983s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.928s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.042s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.290s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.128s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.413s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.750s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.478s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.020m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	53.268s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	57.603s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	50.372s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.031m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	55.223s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	51.071s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	46.537s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	46.996s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	49.495s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	51.107s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	33.778s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.689s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	28.833s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	28.123s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.121s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.836s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.276s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.479s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.962s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.986s		0	1	0.00
		rom_e2e_asm_init_dev	19.567s		0	1	0.00
		rom_e2e_asm_init_prod	14.613s		0	1	0.00
		rom_e2e_asm_init_prod_end	15.296s		0	1	0.00
		rom_e2e_asm_init_rma	12.584s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.550s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.606s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.450s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.812s		0	1	0.00
V2		TOTAL			63	205	30.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.226m	3.552ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.597m	5.036ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.918s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.862s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.676s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.623s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.290m	13.106ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	24.291s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.590m	15.059ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	14.862s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.611s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.918s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.862s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.676s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.215s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.059s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.708s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.122s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	21.428m	16.865ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.328m	3.527ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.117m	4.256ms	1	1	100.00
		chip_plic_all_irqs_0	9.821m	5.532ms	1	1	100.00
		chip_plic_all_irqs_10	10.623m	7.706ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.697m	4.430ms	1	1	100.00
		chip_sw_dma_abort	4.543m	4.055ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.994s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.994s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.626s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.071s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.739s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.455s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.807s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.255s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.696s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.435s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.059m	4.148ms	1	1	100.00
		chip_sw_mbx_smoketest	4.514m	5.468ms	1	1	100.00
		TOTAL			77	250	30.80

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.63193165571435393019509228437133724533732465082284734602548552319643665053922
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 165.250s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.70969887877897810496640001616515954728631166344594044858265056731092491837988
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 116.641s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.95368698854148651290902947571258445465141411364672986071306419336637477481760
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 135.225s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.89376604949535227652115455138093704945512759869039878983880062775047603138556
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 106.681s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.49013315513955855359794629715110488290592505166218537284993908895428582741360
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 102.659s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.109252503673008682584557986655199223877276104953125133005882530080671989487094
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.46580933460413932780987848102491654575816530198880084607071707392560114291396
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.53092339333081012098723154565410397848124604475503422783587709667461880356583
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.63973078347011142084900845158831630357230056972930684917948107038251819732541
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.15141803292827231010399724792097593745220595915744221933956608265978324442758
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.34028474431421547415719354063109545221177823459952828606734426566138240135854
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.42648867675778793616321278449760653255024958149967345534457732106666876639396
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.95846812454023034376898095772726661584192696485173367107905245794027795536688
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.71101074909214026383073660921083000230335237890582998670321536285581316730785
Line 430, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.643342 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.643342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.75516444923482395354695349611411972831471190404293046055975617965854928820287
Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.446895 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.446895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.33192514624984658030909258936358490386081497302683840335705583948778492392462
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.532856 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.532856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.76332703726397936131571467608947054317905259969338810391614471120009845745611
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.920252 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.920252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.52622655892047443398267419516663272236795950838181193185840369701053750763995
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.529872 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.529872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.86978020039346463984313832341309626763939494673528537396391607679486411930671
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.570917 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.570917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.62870330338925639011229904959675655452181569146478803406927512420892766769090
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5724.356381 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (2998590683431896630922019756870609662361820577708898296919789168864821186359270023237518395857932739429611938798397777388890462811847262688617012784356444 [0x3940ce52aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3bf167ea37f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 5724.356381 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.101215669044519365288078332341772989737841535456685633404620180109606406145639
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8387.312358 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (7126932088134730342445855770033462814959784432696693459501784071322929598329273188451818863631967143351644199750000500880389508960600675512446506399784028 [0x8813b7e8aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd30e4507197f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 8387.312358 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.86525647729135769513012790855078333842218093153357902794040281962868756771600
Line 6260, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5097.690567 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: 'h30480000  a_data: 'he87d16af  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h1  a_user: 'h248e3  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5097.690567 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.9274093908406408151511018605564169112769915480957845355063009043839040960770
Line 6260, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5448.015041 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: 'h30480000  a_data: 'h526a05d9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h0  a_user: 'h2696b  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5448.015041 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.85328026426989719332954790614822316373591995248060742908096850103845149671597
    Line 597, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.20954168319028953456097908928299261102499738813720102745009257759295965190801
    Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5308.910051 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5308.910051 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_test_locked0_to_scrap.110583111888537705784721115325439036348401494475773691096785472800392311744680
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.30103888873384010127505231563502116284416549350866453487677694182617826114020
    Line 643, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9855.573159 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9855.573159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.31772977497013598094190289447417613297626555858372009786763042480169685544249
    Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5705.260868 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5705.260868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.108243033893307537523869732368256607995909520317125693702481124170692224191352
    Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4650.218869 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4650.218869 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.96502457140877840333135501740366251622855703766494144609916778883738864050492
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4282.089080 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4282.089080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 0.chip_sw_rv_core_ibex_rnd.60418985763095430596070452042167338342300428383194838297997129194177705906516
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 4789.091215 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 4789.091215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.48685125601105375714447488290667430772891658501058941320524845524136155594779
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6341.505989 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6341.505989 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.19995915981156910390089016132536852744743824025896915586201764407090963671700
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.51045954841777844105127291078466251300951763856049120690127642619425982364479
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3187.666428 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3187.666428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 1 failures:
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.31112884203268965662332494580946022573519933636832430326084117134706684322246
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
  UVM_ERROR @ 12026.938777 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.938777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.82044064561423529540803584433303461392650975849263934018913536879537392841186
    Line 372, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14715.418852 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14715.418852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.5478000937291752811387821897168305729896357811252946967121920399736753812782
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.13420700315831259482012425950561632303330483740687733456649292007280598505722
    Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4054.913110 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4054.913110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```