cf445d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 29.000s | 0 | 1 | 0.00 | |
| V1 | csr_rw | csrng_csr_rw | 20.000s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 34.000s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | csrng_csr_aliasing | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 29.000s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 20.000s | 0 | 1 | 0.00 | |
| csrng_csr_aliasing | 21.000s | 0 | 1 | 0.00 | |||
| V1 | TOTAL | 0 | 6 | 0.00 | |||
| V2 | interrupts | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| V2 | alerts | csrng_alert | 42.000s | 0 | 1 | 0.00 | |
| V2 | err | csrng_err | 43.000s | 0 | 1 | 0.00 | |
| V2 | cmds | csrng_cmds | 21.000s | 0 | 1 | 0.00 | |
| V2 | life cycle | csrng_cmds | 21.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | csrng_stress_all | 29.000s | 0 | 1 | 0.00 | |
| V2 | intr_test | csrng_intr_test | 33.000s | 0 | 1 | 0.00 | |
| V2 | alert_test | csrng_alert_test | 30.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 6.000s | 382.051us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 6.000s | 382.051us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 29.000s | 0 | 1 | 0.00 | |
| csrng_csr_rw | 20.000s | 0 | 1 | 0.00 | |||
| csrng_csr_aliasing | 21.000s | 0 | 1 | 0.00 | |||
| csrng_same_csr_outstanding | 18.000s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 29.000s | 0 | 1 | 0.00 | |
| csrng_csr_rw | 20.000s | 0 | 1 | 0.00 | |||
| csrng_csr_aliasing | 21.000s | 0 | 1 | 0.00 | |||
| csrng_same_csr_outstanding | 18.000s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 1 | 9 | 11.11 | |||
| V2S | tl_intg_err | csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |
| csrng_tl_intg_err | 29.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_config_regwen | csrng_regwen | 43.000s | 0 | 1 | 0.00 | |
| csrng_csr_rw | 20.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_config_mubi | csrng_alert | 42.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 42.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 42.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 21.000s | 0 | 1 | 0.00 | |
| csrng_err | 43.000s | 0 | 1 | 0.00 | |||
| V2S | TOTAL | 0 | 3 | 0.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 30.000s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 1 | 19 | 5.26 |
Job returned non-zero exit code has 18 failures:
Test csrng_smoke has 1 failures.
0.csrng_smoke.112443550190362146938675216776687372297135199525862396397916525313139774190461
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 15, 2025 at 16:36:00 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_cmds has 1 failures.
0.csrng_cmds.66261649285207330770770213843417278696406459790308172035737590204593420734792
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 15, 2025 at 16:36:00 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_stress_all has 1 failures.
0.csrng_stress_all.32137961444202628959702604830489172572968216697839523043415649164902844617616
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 15, 2025 at 16:36:09 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_intr has 1 failures.
0.csrng_intr.95905459405004224443556312813002146676337309751119745089952055142329271570511
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 15, 2025 at 16:36:02 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_alert has 1 failures.
0.csrng_alert.26516315126584795827466155845582052740637466123604268867683490342243010182826
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 15, 2025 at 16:36:23 UTC (total: 00:00:42)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 13 more tests.