EDN Simulation Results

Monday September 15 2025 16:25:37 UTC

GitHub Revision: cf445d0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.810s	23.042us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.750s	60.872us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.750s	19.499us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.290s	179.182us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.100s	131.453us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.100s	336.569us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.750s	19.499us	1	1	100.00
		edn_csr_aliasing	1.100s	131.453us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.340s	49.724us	1	1	100.00
V2	csrng_commands	edn_genbits	1.340s	49.724us	1	1	100.00
V2	genbits	edn_genbits	1.340s	49.724us	1	1	100.00
V2	interrupts	edn_intr	0.840s	22.026us	1	1	100.00
V2	alerts	edn_alert	0.940s	25.230us	1	1	100.00
V2	errs	edn_err	0.890s	51.425us	1	1	100.00
V2	disable	edn_disable	0.720s	34.272us	1	1	100.00
		edn_disable_auto_req_mode	0.860s	94.033us	1	1	100.00
V2	stress_all	edn_stress_all	3.840s	284.168us	1	1	100.00
V2	intr_test	edn_intr_test	0.720s	39.133us	1	1	100.00
V2	alert_test	edn_alert_test	0.810s	44.542us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.350s	101.929us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.350s	101.929us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.750s	60.872us	1	1	100.00
		edn_csr_rw	0.750s	19.499us	1	1	100.00
		edn_csr_aliasing	1.100s	131.453us	1	1	100.00
		edn_same_csr_outstanding	0.920s	36.385us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.750s	60.872us	1	1	100.00
		edn_csr_rw	0.750s	19.499us	1	1	100.00
		edn_csr_aliasing	1.100s	131.453us	1	1	100.00
		edn_same_csr_outstanding	0.920s	36.385us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	2.870s	459.962us	1	1	100.00
		edn_tl_intg_err	1.330s	387.180us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.850s	19.248us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.940s	25.230us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	2.870s	459.962us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	2.870s	459.962us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	2.870s	459.962us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	2.870s	459.962us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.940s	25.230us	1	1	100.00
		edn_sec_cm	2.870s	459.962us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.940s	25.230us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.330s	387.180us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	28.740s	27.662ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00