HMAC Simulation Results

Monday September 15 2025 16:25:37 UTC

GitHub Revision: cf445d0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	5.770s	724.236us	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.770s	151.168us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.760s	17.946us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.670s	2.143ms	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.350s	1.033ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	0.760s	26.944us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.760s	17.946us	1	1	100.00
		hmac_csr_aliasing	5.350s	1.033ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	42.320s	4.674ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	1.186m	7.150ms	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	2.829m	24.246ms	1	1	100.00
		hmac_test_sha384_vectors	18.720s	964.804us	1	1	100.00
		hmac_test_sha512_vectors	18.980s	1.087ms	1	1	100.00
		hmac_test_hmac256_vectors	8.510s	2.818ms	1	1	100.00
		hmac_test_hmac384_vectors	6.770s	2.179ms	1	1	100.00
		hmac_test_hmac512_vectors	9.500s	346.095us	1	1	100.00
V2	burst_wr	hmac_burst_wr	9.250s	513.156us	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	12.443m	25.581ms	1	1	100.00
V2	error	hmac_error	56.680s	25.103ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	17.940s	9.595ms	1	1	100.00
V2	save_and_restore	hmac_smoke	5.770s	724.236us	1	1	100.00
		hmac_long_msg	42.320s	4.674ms	1	1	100.00
		hmac_back_pressure	1.186m	7.150ms	1	1	100.00
		hmac_datapath_stress	12.443m	25.581ms	1	1	100.00
		hmac_burst_wr	9.250s	513.156us	1	1	100.00
		hmac_stress_all	52.990s	4.760ms	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	5.770s	724.236us	1	1	100.00
		hmac_long_msg	42.320s	4.674ms	1	1	100.00
		hmac_back_pressure	1.186m	7.150ms	1	1	100.00
		hmac_datapath_stress	12.443m	25.581ms	1	1	100.00
		hmac_wipe_secret	17.940s	9.595ms	1	1	100.00
		hmac_test_sha256_vectors	2.829m	24.246ms	1	1	100.00
		hmac_test_sha384_vectors	18.720s	964.804us	1	1	100.00
		hmac_test_sha512_vectors	18.980s	1.087ms	1	1	100.00
		hmac_test_hmac256_vectors	8.510s	2.818ms	1	1	100.00
		hmac_test_hmac384_vectors	6.770s	2.179ms	1	1	100.00
		hmac_test_hmac512_vectors	9.500s	346.095us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	5.770s	724.236us	1	1	100.00
		hmac_long_msg	42.320s	4.674ms	1	1	100.00
		hmac_back_pressure	1.186m	7.150ms	1	1	100.00
		hmac_datapath_stress	12.443m	25.581ms	1	1	100.00
		hmac_burst_wr	9.250s	513.156us	1	1	100.00
		hmac_error	56.680s	25.103ms	1	1	100.00
		hmac_wipe_secret	17.940s	9.595ms	1	1	100.00
		hmac_test_sha256_vectors	2.829m	24.246ms	1	1	100.00
		hmac_test_sha384_vectors	18.720s	964.804us	1	1	100.00
		hmac_test_sha512_vectors	18.980s	1.087ms	1	1	100.00
		hmac_test_hmac256_vectors	8.510s	2.818ms	1	1	100.00
		hmac_test_hmac384_vectors	6.770s	2.179ms	1	1	100.00
		hmac_test_hmac512_vectors	9.500s	346.095us	1	1	100.00
		hmac_stress_all	52.990s	4.760ms	1	1	100.00
V2	stress_all	hmac_stress_all	52.990s	4.760ms	1	1	100.00
V2	alert_test	hmac_alert_test	0.550s	14.818us	1	1	100.00
V2	intr_test	hmac_intr_test	0.590s	24.295us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	1.250s	372.079us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	1.250s	372.079us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.770s	151.168us	1	1	100.00
		hmac_csr_rw	0.760s	17.946us	1	1	100.00
		hmac_csr_aliasing	5.350s	1.033ms	1	1	100.00
		hmac_same_csr_outstanding	1.310s	143.878us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.770s	151.168us	1	1	100.00
		hmac_csr_rw	0.760s	17.946us	1	1	100.00
		hmac_csr_aliasing	5.350s	1.033ms	1	1	100.00
		hmac_same_csr_outstanding	1.310s	143.878us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	tl_intg_err	hmac_sec_cm	19.746s		0	1	0.00
		hmac_tl_intg_err	3.220s	293.217us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.220s	293.217us	1	1	100.00
V2S		TOTAL			1	2	50.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	5.770s	724.236us	1	1	100.00
V3	stress_reset	hmac_stress_reset	4.670s	129.232us	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	54.030s	16.108ms	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	5.050s	513.910us	1	1	100.00
		TOTAL			27	28	96.43

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test hmac_sec_cm has 1 failures.

    • 0.hmac_sec_cm.4881424352619063183604952965032648677319537239121674335808342343827282750694
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_sec_cm/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 15 16:29 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255