cf445d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 16.070s | 4.888ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 22.130s | 4.293ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.640s | 25.750us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.610s | 56.366us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.250s | 1.384ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.390s | 154.126us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.020s | 45.959us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.610s | 56.366us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 1.390s | 154.126us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 7 | 7 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0.760s | 25.075us | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 0.840s | 97.456us | 0 | 1 | 0.00 |
| V2 | host_maxperf | i2c_host_perf | 2.730s | 809.691us | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 0.640s | 26.325us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 2.993m | 17.498ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 22.070s | 23.526ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0.880s | 710.340us | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 14.890s | 935.850us | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 2.910s | 184.177us | 1 | 1 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 1.142m | 7.232ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 10.840s | 4.402ms | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.130s | 376.411us | 1 | 1 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 2.010s | 1.078ms | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 18.260s | 0 | 1 | 0.00 | |
| V2 | target_maxperf | i2c_target_perf | 26.266s | 0 | 1 | 0.00 | |
| V2 | target_fifo_empty | i2c_target_stress_rd | 4.330s | 322.530us | 1 | 1 | 100.00 |
| i2c_target_intr_smoke | 3.590s | 3.313ms | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.140s | 274.292us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 0.820s | 486.341us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 5.055m | 59.798ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 4.330s | 322.530us | 1 | 1 | 100.00 | ||
| i2c_target_intr_stress_wr | 18.680s | 12.286ms | 1 | 1 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 4.060s | 1.429ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 9.230s | 5.202ms | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 3.630s | 2.002ms | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.390s | 1.570ms | 1 | 1 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 1.930s | 1.145ms | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 0.930s | 1.554ms | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 2.730s | 809.691us | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 1.460s | 320.993us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 10.840s | 4.402ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 11.957s | 0 | 1 | 0.00 | |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 1.970s | 1.330ms | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.440s | 1.470ms | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 18.005s | 0 | 1 | 0.00 | |||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 11.950s | 472.847us | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 1.550s | 590.324us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.590s | 29.317us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.640s | 28.454us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.730s | 48.544us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.730s | 48.544us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.640s | 25.750us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.610s | 56.366us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.390s | 154.126us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 17.042s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.640s | 25.750us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.610s | 56.366us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.390s | 154.126us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 17.042s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 30 | 38 | 78.95 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.530s | 176.209us | 1 | 1 | 100.00 |
| i2c_sec_cm | 0.760s | 53.116us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.530s | 176.209us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 20.700s | 820.100us | 0 | 1 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 24.160s | 0 | 1 | 0.00 | |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 6.550s | 819.840us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 39 | 50 | 78.00 |
Job returned non-zero exit code has 6 failures:
Test i2c_target_unexp_stop has 1 failures.
0.i2c_target_unexp_stop.84900707891492532260512205945400580477634338747138879516134898790716765423167
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_perf has 1 failures.
0.i2c_target_perf.27072398175495950006259423594198862858650089468737546504770059695115062489841
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_stress_all has 1 failures.
0.i2c_target_stress_all.6221856870312685813505196065860674040985336753617380128422103452988261909131
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_tx_stretch_ctrl has 1 failures.
0.i2c_target_tx_stretch_ctrl.96110367767099314237438792906410341081700443261778092660633422385690141966272
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_nack_txstretch has 1 failures.
0.i2c_target_nack_txstretch.20015244701293933413923755960997009105440689821877508302925270272274630204436
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more tests.
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:
Test i2c_host_error_intr has 1 failures.
0.i2c_host_error_intr.104031274192530023680608048322790453695366394003218871354662923834805892785720
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 25074768 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 25074768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
0.i2c_host_stress_all.18540997354837459319054860518398734560262065419873676472813429907929048481265
Line 113, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 97455979 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 97455979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.68747596877066047358891644109263069735615632596703375244982090315700239130879
Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 819839557 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 819839557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.48203628639802266543649889172319366340449402252815937741913720014807010299010
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 1078440496 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1078440496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.i2c_host_stress_all_with_rand_reset.8260465233339935219648167869997726906635589309508078835119439631876298841671
Line 88, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 820100274 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 820100274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---