KEYMGR Simulation Results

Monday September 15 2025 16:25:37 UTC

GitHub Revision: cf445d0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	8.420s	6.839ms	1	1	100.00
V1	random	keymgr_random	16.027s		0	1	0.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.940s	61.275us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	20.413s		0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	4.940s	137.075us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.370s	251.487us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.020s	45.711us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	20.413s		0	1	0.00
		keymgr_csr_aliasing	4.370s	251.487us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	1.650s	112.268us	1	1	100.00
V2	sideload	keymgr_sideload	4.730s	652.803us	1	1	100.00
		keymgr_sideload_kmac	2.250s	215.180us	1	1	100.00
		keymgr_sideload_aes	20.370s	1.446ms	1	1	100.00
		keymgr_sideload_otbn	1.790s	106.000us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.460s	30.885us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	1.890s	118.056us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.280s	365.222us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.350s	1.315ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.740s	569.092us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	8.800s	973.557us	1	1	100.00
V2	stress_all	keymgr_stress_all	15.230s	6.728ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.640s	22.573us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.650s	58.372us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.470s	59.356us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.470s	59.356us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.940s	61.275us	1	1	100.00
		keymgr_csr_rw	20.413s		0	1	0.00
		keymgr_csr_aliasing	4.370s	251.487us	1	1	100.00
		keymgr_same_csr_outstanding	2.020s	358.832us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.940s	61.275us	1	1	100.00
		keymgr_csr_rw	20.413s		0	1	0.00
		keymgr_csr_aliasing	4.370s	251.487us	1	1	100.00
		keymgr_same_csr_outstanding	2.020s	358.832us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
		keymgr_tl_intg_err	1.810s	78.610us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.600s	254.177us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.600s	254.177us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.600s	254.177us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.600s	254.177us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.180s	351.863us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.810s	78.610us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.600s	254.177us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.650s	112.268us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	16.027s		0	1	0.00
		keymgr_csr_rw	20.413s		0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	16.027s		0	1	0.00
		keymgr_csr_rw	20.413s		0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	16.027s		0	1	0.00
		keymgr_csr_rw	20.413s		0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	1.890s	118.056us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.740s	569.092us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.740s	569.092us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	16.027s		0	1	0.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.120s	611.922us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.120s	1.415ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	1.890s	118.056us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.120s	1.415ms	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.120s	1.415ms	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.120s	1.415ms	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.330s	352.414us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.120s	1.415ms	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.670s	428.533us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test keymgr_random has 1 failures.

    • 0.keymgr_random.62408891039955262710996468109687902147199068320127243808106603518580882545225
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_random/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 15 16:28 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.85290463417771334125787481449317318165824666126503537003084436861554227090364
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 15 16:28 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255