cf445d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 34.360s | 14.348ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | kmac_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | kmac_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | kmac_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0 | 1 | 0.00 | ||
| kmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | mem_walk | kmac_mem_walk | 0 | 1 | 0.00 | ||
| V1 | mem_partial_access | kmac_mem_partial_access | 0 | 1 | 0.00 | ||
| V1 | TOTAL | 1 | 8 | 12.50 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 33.408m | 104.100ms | 1 | 1 | 100.00 |
| V2 | burst_write | kmac_burst_write | 9.954m | 104.997ms | 1 | 1 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 22.980s | 617.267us | 1 | 1 | 100.00 |
| kmac_test_vectors_sha3_256 | 20.482m | 721.229ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 18.021m | 135.217ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 20.603s | 0 | 1 | 0.00 | |||
| kmac_test_vectors_shake_128 | 2.252m | 9.970ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.625m | 46.851ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac | 1.240s | 91.976us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 1.860s | 106.856us | 1 | 1 | 100.00 | ||
| V2 | sideload | kmac_sideload | 1.993m | 6.829ms | 1 | 1 | 100.00 |
| V2 | app | kmac_app | 1.922m | 30.048ms | 1 | 1 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 1.519m | 7.203ms | 1 | 1 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 2.818m | 59.147ms | 1 | 1 | 100.00 |
| V2 | error | kmac_error | 16.290s | 4.548ms | 1 | 1 | 100.00 |
| V2 | key_error | kmac_key_error | 1.400s | 234.638us | 1 | 1 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 2.180s | 138.175us | 1 | 1 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 13.590s | 1.073ms | 1 | 1 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 19.650s | 872.802us | 1 | 1 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 6.750s | 869.986us | 1 | 1 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 15.659s | 0 | 1 | 0.00 | |
| V2 | stress_all | kmac_stress_all | 16.922m | 266.860ms | 1 | 1 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0 | 1 | 0.00 | ||
| V2 | alert_test | kmac_alert_test | 0.700s | 30.949us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | kmac_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| kmac_csr_rw | 0 | 1 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| kmac_csr_rw | 0 | 1 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 21 | 26 | 80.77 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 0 | 1 | 0.00 | ||
| V2S | tl_intg_err | kmac_sec_cm | 14.740s | 6.002ms | 1 | 1 | 100.00 |
| kmac_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 15.659s | 0 | 1 | 0.00 | |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 34.360s | 14.348ms | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 1.993m | 6.829ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 14.740s | 6.002ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 14.740s | 6.002ms | 1 | 1 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 14.740s | 6.002ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 34.360s | 14.348ms | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 15.659s | 0 | 1 | 0.00 | |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 14.740s | 6.002ms | 1 | 1 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 22.766s | 0 | 1 | 0.00 | |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 34.360s | 14.348ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 5 | 20.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 27.450s | 2.895ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 24 | 40 | 60.00 |
Job killed most likely because its dependent job failed. has 13 failures:
Test kmac_shadow_reg_errors has 1 failures.
Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
Test kmac_mem_walk has 1 failures.
Test kmac_mem_partial_access has 1 failures.
Test kmac_tl_errors has 1 failures.
... and 8 more tests.
Job returned non-zero exit code has 3 failures:
Test kmac_test_vectors_sha3_512 has 1 failures.
0.kmac_test_vectors_sha3_512.83747506401993629371081571104869183477867895555934324858342099883955545332751
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:28 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_mubi has 1 failures.
0.kmac_mubi.23665529825563093744145851200844230364355324838562377384885851885566205690841
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mubi/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_lc_escalation has 1 failures.
0.kmac_lc_escalation.51249002104477707830885902377285355470839830190123710131824337635941346995393
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Job timed out after * minutes has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/build.log
Job timed out after 60 minutes