ROM_CTRL/32KB Simulation Results

Monday September 15 2025 16:25:37 UTC

GitHub Revision: cf445d0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.130s	573.989us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.830s	181.028us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.110s	144.960us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.610s	553.338us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	2.820s	336.000us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset			0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.110s	144.960us	1	1	100.00
		rom_ctrl_csr_aliasing	2.820s	336.000us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.280s	128.620us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.770s	173.756us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	3.490s	230.899us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	10.120s	340.675us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	15.949s		0	1	0.00
V2	alert_test	rom_ctrl_alert_test	3.270s	725.954us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.780s	2.948ms	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.780s	2.948ms	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.830s	181.028us	1	1	100.00
		rom_ctrl_csr_rw	3.110s	144.960us	1	1	100.00
		rom_ctrl_csr_aliasing	2.820s	336.000us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.410s	800.187us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.830s	181.028us	1	1	100.00
		rom_ctrl_csr_rw	3.110s	144.960us	1	1	100.00
		rom_ctrl_csr_aliasing	2.820s	336.000us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.410s	800.187us	1	1	100.00
V2		TOTAL			5	6	83.33
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	18.290s	7.802ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.541m	834.139us	0	1	0.00
		rom_ctrl_tl_intg_err	22.590s	268.252us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.541m	834.139us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.541m	834.139us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.541m	834.139us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.541m	834.139us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.130s	573.989us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.130s	573.989us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.130s	573.989us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	22.590s	268.252us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
		rom_ctrl_kmac_err_chk	15.949s		0	1	0.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.580s	221.991us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	18.290s	7.802ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.541m	834.139us	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.007m	1.600ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			15	19	78.95

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.31374946024932921697450490431003893056465106521011041696453784011916222474731
      Line 79, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 221990970 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 221990970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 0.rom_ctrl_kmac_err_chk.66619784859366788775833895263859767011647874749432202065364640175615640249994
      Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 15 16:36 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.8768328140275020077465761710420618754467294290028911634270275305417928143458
      Line 230, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 29716336ps failed at 29716336ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 29735567ps failed at 29735567ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

• Job timed out after * minutes has 1 failures:

  • Test rom_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rom_ctrl_csr_mem_rw_with_rand_reset.32143605479346759910753367980160590962769668891452782169116980517394533189099
      Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        Job timed out after 60 minutes