cf445d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 20.386s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 9.120s | 297.593us | 1 | 1 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 6.320s | 1.031ms | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 15.623s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 5.400s | 539.858us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 5.690s | 390.003us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 6.320s | 1.031ms | 1 | 1 | 100.00 |
| rom_ctrl_csr_aliasing | 5.400s | 539.858us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 5.640s | 214.867us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 5.640s | 212.685us | 1 | 1 | 100.00 |
| V1 | TOTAL | 6 | 8 | 75.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 6.320s | 1.775ms | 1 | 1 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 21.210s | 843.724us | 1 | 1 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 14.010s | 546.689us | 1 | 1 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 15.671s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 7.850s | 1.499ms | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 7.850s | 1.499ms | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 9.120s | 297.593us | 1 | 1 | 100.00 |
| rom_ctrl_csr_rw | 6.320s | 1.031ms | 1 | 1 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.400s | 539.858us | 1 | 1 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.030s | 292.609us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 9.120s | 297.593us | 1 | 1 | 100.00 |
| rom_ctrl_csr_rw | 6.320s | 1.031ms | 1 | 1 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.400s | 539.858us | 1 | 1 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.030s | 292.609us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 25.910s | 1.059ms | 1 | 1 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 7.064m | 5.962ms | 0 | 1 | 0.00 |
| rom_ctrl_tl_intg_err | 49.350s | 725.474us | 1 | 1 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 7.064m | 5.962ms | 0 | 1 | 0.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 7.064m | 5.962ms | 0 | 1 | 0.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 7.064m | 5.962ms | 0 | 1 | 0.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 7.064m | 5.962ms | 0 | 1 | 0.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 20.386s | 0 | 1 | 0.00 | |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 20.386s | 0 | 1 | 0.00 | |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 20.386s | 0 | 1 | 0.00 | |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 49.350s | 725.474us | 1 | 1 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| rom_ctrl_kmac_err_chk | 14.010s | 546.689us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 2.224m | 14.866ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 25.910s | 1.059ms | 1 | 1 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 7.064m | 5.962ms | 0 | 1 | 0.00 |
| V2S | TOTAL | 3 | 4 | 75.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 1.474m | 30.013ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 15 | 19 | 78.95 |
Job returned non-zero exit code has 3 failures:
Test rom_ctrl_smoke has 1 failures.
0.rom_ctrl_smoke.99972346439475503778086994610750365852081048181047730875811526701126732557256
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:41 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_alert_test has 1 failures.
0.rom_ctrl_alert_test.62865017235426659671068794194786564121189641345702334515617429968353824770548
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:41 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_csr_bit_bash has 1 failures.
0.rom_ctrl_csr_bit_bash.43987044301310111505173818482325356961540912824079421386837356639119962486748
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:40 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
0.rom_ctrl_sec_cm.71293956172424290381792375363451797779739771075455540612312389986957535768304
Line 108, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 22857254ps failed at 22857254ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 22857254ps failed at 22857254ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'