RV_TIMER Simulation Results

Monday September 15 2025 16:25:37 UTC

GitHub Revision: cf445d0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.560s	37.962us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.550s	97.207us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.500s	34.482us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.170s	71.458us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.630s	215.910us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	14.028s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.500s	34.482us	1	1	100.00
		rv_timer_csr_aliasing	0.630s	215.910us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	random_reset	rv_timer_random_reset	6.360s	40.282ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.030s	1.684ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.551m	1.096s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.551m	1.096s	1	1	100.00
V2	stress	rv_timer_stress_all	1.060s	2.239ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.550s	50.797us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.540s	52.670us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.610s	461.692us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.610s	461.692us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.550s	97.207us	1	1	100.00
		rv_timer_csr_rw	0.500s	34.482us	1	1	100.00
		rv_timer_csr_aliasing	0.630s	215.910us	1	1	100.00
		rv_timer_same_csr_outstanding	0.680s	62.701us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.550s	97.207us	1	1	100.00
		rv_timer_csr_rw	0.500s	34.482us	1	1	100.00
		rv_timer_csr_aliasing	0.630s	215.910us	1	1	100.00
		rv_timer_same_csr_outstanding	0.680s	62.701us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	0.850s	191.023us	1	1	100.00
		rv_timer_tl_intg_err	0.760s	515.219us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.760s	515.219us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	18.067s		0	1	0.00
V3	max_value	rv_timer_max	0.550s	15.105us	1	1	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	32.450s	58.653ms	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			17	19	89.47

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.28421272154837688093953758654732470848023791542908717204929246851470592914543
      Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 15 16:38 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test rv_timer_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rv_timer_csr_mem_rw_with_rand_reset.33843926947632574661714432698802141117283620873192895222158872517496866827097
      Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 15 16:37 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255