cf445d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.050s | 154.720us | 1 | 1 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 1.010s | 20.949us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 14.166s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | spi_device_csr_aliasing | 5.610s | 313.601us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 1.890s | 71.554us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 1.010s | 20.949us | 1 | 1 | 100.00 |
| spi_device_csr_aliasing | 5.610s | 313.601us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.630s | 32.017us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.060s | 417.639us | 1 | 1 | 100.00 |
| V1 | TOTAL | 6 | 8 | 75.00 | |||
| V2 | csb_read | spi_device_csb_read | 0 | 1 | 0.00 | ||
| V2 | mem_parity | spi_device_mem_parity | 0 | 1 | 0.00 | ||
| V2 | mem_cfg | spi_device_ram_cfg | 0 | 1 | 0.00 | ||
| V2 | tpm_read | spi_device_tpm_rw | 0 | 1 | 0.00 | ||
| V2 | tpm_write | spi_device_tpm_rw | 0 | 1 | 0.00 | ||
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 0 | 1 | 0.00 | ||
| spi_device_tpm_sts_read | 0 | 1 | 0.00 | ||||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 0 | 1 | 0.00 | ||
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | cmd_info_slots | spi_device_flash_all | 0 | 1 | 0.00 | ||
| V2 | cmd_read_status | spi_device_intercept | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | cmd_read_jedec | spi_device_intercept | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | cmd_read_sfdp | spi_device_intercept | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | cmd_fast_read | spi_device_intercept | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | cmd_read_pipeline | spi_device_intercept | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | flash_cmd_upload | spi_device_upload | 0 | 1 | 0.00 | ||
| V2 | mailbox_command | spi_device_mailbox | 0 | 1 | 0.00 | ||
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 0 | 1 | 0.00 | ||
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 0 | 1 | 0.00 | ||
| V2 | cmd_read_buffer | spi_device_flash_mode | 0 | 1 | 0.00 | ||
| spi_device_read_buffer_direct | 0 | 1 | 0.00 | ||||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 0 | 1 | 0.00 | ||
| spi_device_flash_all | 0 | 1 | 0.00 | ||||
| V2 | quad_spi | spi_device_flash_all | 0 | 1 | 0.00 | ||
| V2 | dual_spi | spi_device_flash_all | 0 | 1 | 0.00 | ||
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 0 | 1 | 0.00 | ||
| V2 | write_enable_disable | spi_device_cfg_cmd | 0 | 1 | 0.00 | ||
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 0 | 1 | 0.00 | ||
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 0 | 1 | 0.00 | ||
| V2 | stress_all | spi_device_stress_all | 0 | 1 | 0.00 | ||
| V2 | alert_test | spi_device_alert_test | 0 | 1 | 0.00 | ||
| V2 | intr_test | spi_device_intr_test | 0.640s | 30.031us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 2.530s | 226.160us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 2.530s | 226.160us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.050s | 154.720us | 1 | 1 | 100.00 |
| spi_device_csr_rw | 1.010s | 20.949us | 1 | 1 | 100.00 | ||
| spi_device_csr_aliasing | 5.610s | 313.601us | 1 | 1 | 100.00 | ||
| spi_device_same_csr_outstanding | 14.418s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.050s | 154.720us | 1 | 1 | 100.00 |
| spi_device_csr_rw | 1.010s | 20.949us | 1 | 1 | 100.00 | ||
| spi_device_csr_aliasing | 5.610s | 313.601us | 1 | 1 | 100.00 | ||
| spi_device_same_csr_outstanding | 14.418s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 2 | 22 | 9.09 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 0 | 1 | 0.00 | ||
| spi_device_tl_intg_err | 12.950s | 304.332us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 12.950s | 304.332us | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| Unmapped tests | spi_device_flash_mode_ignore_cmds | 0 | 1 | 0.00 | |||
| TOTAL | 9 | 33 | 27.27 |
Job killed most likely because its dependent job failed. has 22 failures:
Test spi_device_csb_read has 1 failures.
Test spi_device_mem_parity has 1 failures.
Test spi_device_ram_cfg has 1 failures.
Test spi_device_tpm_read_hw_reg has 1 failures.
Test spi_device_tpm_all has 1 failures.
... and 17 more tests.
Job returned non-zero exit code has 2 failures:
Test spi_device_csr_bit_bash has 1 failures.
0.spi_device_csr_bit_bash.86491471598277037001254686846892617490342515478942946430030505152619265695578
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test spi_device_same_csr_outstanding has 1 failures.
0.spi_device_same_csr_outstanding.18926680648038050870533724444983614428509253257845549488235850991304170329747
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 15 16:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Job timed out after * minutes has 1 failures:
default
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/default/build.log
Job timed out after 60 minutes