SRAM_CTRL/RET Simulation Results

Monday September 15 2025 16:25:37 UTC

GitHub Revision: cf445d0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.770s	222.439us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.640s	43.867us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.600s	15.634us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.210s	351.592us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	30.864s		0	1	0.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.780s	47.404us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.600s	15.634us	1	1	100.00
		sram_ctrl_csr_aliasing	30.864s		0	1	0.00
V1	mem_walk	sram_ctrl_mem_walk	7.530s	2.507ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.300s	185.591us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	3.865m	3.377ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.607m	3.488ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	32.070s	10.580ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.209m	1.845ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.750s	379.587us	1	1	100.00
V2	executable	sram_ctrl_executable	4.061m	12.278ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	40.530s	6.562ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.035m	13.942ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	14.480s	694.212us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	35.420s	303.849us	1	1	100.00
		sram_ctrl_throughput_w_readback	33.530s	492.003us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.559m	9.643ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.670s	29.830us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	19.624m	171.019ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.620s	21.406us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.910s	604.167us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.910s	604.167us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.640s	43.867us	1	1	100.00
		sram_ctrl_csr_rw	0.600s	15.634us	1	1	100.00
		sram_ctrl_csr_aliasing	30.864s		0	1	0.00
		sram_ctrl_same_csr_outstanding	0.700s	21.925us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.640s	43.867us	1	1	100.00
		sram_ctrl_csr_rw	0.600s	15.634us	1	1	100.00
		sram_ctrl_csr_aliasing	30.864s		0	1	0.00
		sram_ctrl_same_csr_outstanding	0.700s	21.925us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.400s	282.781us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.700s	16.539us	0	1	0.00
		sram_ctrl_tl_intg_err	1.760s	178.224us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.700s	16.539us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.760s	178.224us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.559m	9.643ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.559m	9.643ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.600s	15.634us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.061m	12.278ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.061m	12.278ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.061m	12.278ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.750s	379.587us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.780s	35.529us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.400s	282.781us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.780s	58.212us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.770s	222.439us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.770s	222.439us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.061m	12.278ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.700s	16.539us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.750s	379.587us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.700s	16.539us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.700s	16.539us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.770s	222.439us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.700s	16.539us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.405m	3.914ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.59532251666174448822437928032623719360359529610410281993950345518275384007654
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  16539302 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  16539302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test sram_ctrl_csr_aliasing has 1 failures.

    • 0.sram_ctrl_csr_aliasing.77111018670067565879814845306874336589083904872339482676515188899187788315434
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest/run.log

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