CHIP Simulation Results

Monday September 15 2025 16:25:37 UTC

GitHub Revision: cf445d0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.071s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.071s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	17.363s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.588s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	17.672s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	14.673s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	14.673s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	14.673s		0	1	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	14.222s		0	1	0.00
		chip_sw_example_manufacturer	14.223s		0	1	0.00
		chip_sw_example_concurrency	14.237s		0	1	0.00
		chip_sw_uart_smoketest_signed	19.700s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	7.890s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing			0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	1	0.00
V1	xbar_smoke	xbar_smoke			0	1	0.00
V1		TOTAL			0	12	0.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	10.273s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.734s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	15.756s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	17.921s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	18.028s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	18.517s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	15.182s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.680s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.680s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	13.547s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	12.351s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.078s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.078s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.462m	5.448ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	1.938m	3.412ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	10.317s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.172s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.223s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	26.609s		0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	18.871s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	18.145s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	18.145s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.567s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.646s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.646s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	18.664s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	15.207s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.763s		0	1	0.00
		chip_sw_aes_idle	14.816s		0	1	0.00
		chip_sw_hmac_enc_idle	19.638s		0	1	0.00
		chip_sw_kmac_idle	19.228s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.769s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.387s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	15.225s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	15.224s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	14.673s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.790s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.906s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.181s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.631s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.246s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.688s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.673s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.790s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.906s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.181s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.631s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.246s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.688s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	15.006s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.414s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	20.253s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	19.196s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.068s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.615s		0	1	0.00
		chip_sw_clkmgr_jitter	13.127s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	15.106s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	15.777s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	14.722s		0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	14.722s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	15.328s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	15.161s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	14.273s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	15.270s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.624s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.343s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.687s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.257s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	20.195s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	17.646s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	17.790s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	20.195s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	19.729s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	19.618s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	20.079s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	20.066s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	19.520s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.257s		0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	10.317s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	15.222s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.283s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	20.763s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	10.265s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.257s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.120s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.573s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.257s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.568s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	20.763s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.567s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.557s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.981s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.626s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.688s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.634s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.573s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.083s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	19.255s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.978s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.607s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.363s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.702s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	20.363s		0	1	0.00
		chip_sw_rom_ctrl_integrity_check	18.685s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	18.250s		0	1	0.00
		chip_prim_tl_access	6.812m	11.089ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.673s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.790s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.906s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.181s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.631s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.246s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.688s		0	1	0.00
		chip_rv_dm_lc_disabled	26.609s		0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	15.062s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.414s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	14.565s		0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	14.816s		0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	18.889s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	20.253s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	19.638s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	19.682s		0	1	0.00
		chip_sw_kmac_mode_kmac	18.697s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.068s		0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	20.363s		0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	19.665s		0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.286s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	19.228s		0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.308s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.308s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	20.267s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	10.320s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	10.228s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	20.363s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	19.196s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	10.129s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	15.006s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.763s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.763s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.763s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	15.185s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	18.685s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	18.685s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	18.197s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.615s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.250s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.257s		0	1	0.00
		chip_sw_data_integrity_escalation	14.078s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	15.185s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	20.363s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	18.197s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	15.273s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	15.185s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	20.363s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	18.197s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	15.273s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.166s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.083s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.978s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.607s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.363s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.702s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.657s		0	1	0.00
		chip_prim_tl_access	6.812m	11.089ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.812m	11.089ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	15.391s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	13.717s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.624s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	15.006s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.414s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	20.253s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	19.196s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.068s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.615s		0	1	0.00
		chip_sw_clkmgr_jitter	13.127s		0	1	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	18.591s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	18.591s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	18.682s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	18.585s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	18.674s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	15.425s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	15.243s		0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	14.887s		0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	15.273s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	15.222s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	15.222s		0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	19.475s		0	1	0.00
		chip_sw_aon_timer_smoketest	18.487s		0	1	0.00
		chip_sw_clkmgr_smoketest	18.693s		0	1	0.00
		chip_sw_csrng_smoketest	18.327s		0	1	0.00
		chip_sw_gpio_smoketest	18.425s		0	1	0.00
		chip_sw_hmac_smoketest	18.632s		0	1	0.00
		chip_sw_kmac_smoketest	17.641s		0	1	0.00
		chip_sw_otbn_smoketest	10.259s		0	1	0.00
		chip_sw_otp_ctrl_smoketest	10.303s		0	1	0.00
		chip_sw_rv_plic_smoketest	10.297s		0	1	0.00
		chip_sw_rv_timer_smoketest	10.342s		0	1	0.00
		chip_sw_rstmgr_smoketest	10.441s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	10.280s		0	1	0.00
		chip_sw_uart_smoketest	10.206s		0	1	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	19.739s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	19.700s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	10.273s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	14.494s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	14.302s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	13.294s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	12.341s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	11.863s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.160s		0	1	0.00
		chip_rv_dm_lc_disabled	26.609s		0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.233s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.388s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.280s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.819s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.160s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.760s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.965s		0	1	0.00
		rom_volatile_raw_unlock	19.294s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	19.656s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	14.906s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	10.140s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.047m	4.052ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.047m	4.052ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding	8.140s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding	8.140s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random			0	1	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	1	0.00
		xbar_smoke_large_delays			0	1	0.00
		xbar_smoke_slow_rsp			0	1	0.00
		xbar_random_zero_delays			0	1	0.00
		xbar_random_large_delays			0	1	0.00
		xbar_random_slow_rsp			0	1	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	1	0.00
		xbar_error_and_unmapped_addr			0	1	0.00
V2	xbar_error_cases	xbar_error_random			0	1	0.00
		xbar_error_and_unmapped_addr			0	1	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	1	0.00
		xbar_access_same_device_slow_rsp			0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	1	0.00
V2	xbar_stress_all	xbar_stress_all			0	1	0.00
		xbar_stress_all_with_error			0	1	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	1	0.00
		xbar_stress_all_with_reset_error			0	1	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.033s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.126s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.499s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.241s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.204s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.098s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.103s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.154s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.205s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.308s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	15.076s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.199s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.690s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	14.358s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	14.578s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	14.575s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	14.249s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	14.085s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	14.989s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.815s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	10.591s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	10.486s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	10.531s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	10.323s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	10.424s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	10.584s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	10.315s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	10.424s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	10.321s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	10.679s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.480s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.712s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.374s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	14.662s		0	1	0.00
		rom_e2e_asm_init_dev	14.616s		0	1	0.00
		rom_e2e_asm_init_prod	14.450s		0	1	0.00
		rom_e2e_asm_init_prod_end	14.105s		0	1	0.00
		rom_e2e_asm_init_rma	14.118s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.244s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.078s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.285s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.138s		0	1	0.00
V2		TOTAL			1	205	0.49
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	15.178s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	15.609s		0	1	0.00
V2S		TOTAL			0	2	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	14.126s		0	1	0.00
		rom_e2e_jtag_debug_dev	14.200s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.095s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.273s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.257s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.250s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	14.628s		0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	15.613s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.104s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	14.126s		0	1	0.00
		rom_e2e_jtag_debug_dev	14.200s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.095s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	13.692s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.542s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.235s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	14.415s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	14.131s		0	1	0.00
		chip_sw_entropy_src_kat_test	19.879s		0	1	0.00
		chip_sw_entropy_src_ast_rng_req	19.221s		0	1	0.00
		chip_plic_all_irqs_0	10.202s		0	1	0.00
		chip_plic_all_irqs_10	14.493s		0	1	0.00
		chip_sw_dma_inline_hashing	14.549s		0	1	0.00
		chip_sw_dma_abort	13.997s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.128s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.282s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.126s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.057s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.108s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.219s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.102s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.157s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	19.768s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.157s		0	1	0.00
		chip_sw_entropy_src_smoketest	18.374s		0	1	0.00
		chip_sw_mbx_smoketest	17.798s		0	1	0.00
		TOTAL			1	250	0.40

Failure Buckets

• Job returned non-zero exit code has 225 failures:

  • Test xbar_build_mode has 1 failures.

    • xbar_build_mode
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/build.log

        recompiling module tb
        All of 632 modules done
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        CPU time: 153.107 seconds to compile
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
      

  • Test chip_sw_example_rom has 1 failures.

    • 0.chip_sw_example_rom.77793322095681023169591392699087346068603113322927582315743593529299488764555
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

                    done; \
                fi; \
            fi; \
        done;
        Building SW image "//sw/device/tests:example_test_from_rom_sim_dv".
        Building "//sw/device/tests:example_test_from_rom_sim_dv" on network connected machine.
        Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_rom_sim_dv
        Computing main repo mapping:
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

  • Test chip_sw_example_manufacturer has 1 failures.

    • 0.chip_sw_example_manufacturer.87506144116792954731856254571725865399122120491862579237060997106181197866931
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

                fi; \
            fi; \
        done;
        Building SW image "@manufacturer_test_hooks//:example_test_sim_dv".
        Building "@manufacturer_test_hooks//:example_test_sim_dv" on network connected machine.
        Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true @manufacturer_test_hooks//:example_test_sim_dv
        Another command (pid=891392) is running. Waiting for it to complete on the server (server_pid=887169)...
        Computing main repo mapping:
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

  • Test chip_sw_example_concurrency has 1 failures.

    • 0.chip_sw_example_concurrency.63032390079848415398750253325942903553163024175877680970654710817479770499799
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

        Another command holds the output base lock:
        pid=891751
        owner=client
        cwd=/nightly/current_run/opentitan
      
        Waiting for it to complete...
        Another command (pid=891392) is running. Waiting for it to complete on the server (server_pid=887169)...
        Computing main repo mapping:
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/bazel_skylib/1.7.1/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

  • Test chip_sw_all_escalation_resets has 1 failures.

    • 0.chip_sw_all_escalation_resets.61409567926650334835261074349992070688386409390628991473334459543223133855410
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

            fi; \
        done;
        Building SW image "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv".
        Building "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv" on network connected machine.
        Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv
        Another command (pid=891392) is running. Waiting for it to complete on the server (server_pid=887169)...
        Another command (pid=891762) is running. Waiting for it to complete on the server (server_pid=887169)...
        Computing main repo mapping:
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/googletest/1.14.0.bcr.1/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

  • ... and 220 more tests.

• Job killed most likely because its dependent job failed. has 18 failures:

  • Test xbar_smoke has 1 failures.

    • 0.xbar_smoke.10011806399771248745606873090029986087770695094965277586525963271766738736897
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke/latest/run.log

  • Test xbar_smoke_zero_delays has 1 failures.

    • 0.xbar_smoke_zero_delays.42591598729854488742339174252977491917440759801093978264589948349376388580440
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log

  • Test xbar_smoke_large_delays has 1 failures.

    • 0.xbar_smoke_large_delays.75418008079006478815980745196601463023846951064839988658847345933645153308979
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log

  • Test xbar_smoke_slow_rsp has 1 failures.

    • 0.xbar_smoke_slow_rsp.58408187748873129070081163807585644272931203658964884683038951926539595361377
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log

  • Test xbar_random has 1 failures.

    • 0.xbar_random.72471170257081461271687887637363724836208046759893580843057046755532858305135
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random/latest/run.log

  • ... and 13 more tests.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 2 failures:

  • Test chip_csr_bit_bash has 1 failures.

    • 0.chip_csr_bit_bash.111182680496468047950272678885755982477352018383049766738738530971217100837868
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_same_csr_outstanding has 1 failures.

    • 0.chip_same_csr_outstanding.30382460487686871385301852431747190007416739852963795996039431985511919299394
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

  • Test chip_jtag_csr_rw has 1 failures.

    • 0.chip_jtag_csr_rw.16161440038577413686436827317034408447600805896264262995263865714344650349431
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 5448.101030 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'hc2e6a36e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h1  a_user: 'h248ea  d_param: 'h0  d_source: 'hc  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 5448.101030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_jtag_mem_access has 1 failures.

    • 0.chip_jtag_mem_access.39287974716860331764650824376120817447263627423122747936765402152317628989555
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 3411.913296 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'h1646f81f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h0  a_user: 'h2690e  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3411.913296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test chip_csr_aliasing has 1 failures.

    • 0.chip_csr_aliasing.108267162415516853883708430614052490461841936967518494470440246767601400054811
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        Job timed out after 180 minutes
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36821) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.49744504485799817943381789134218922574940761116424324001256438159357855953894
      Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

        UVM_ERROR @ 4052.122735 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36821) { a_addr: 'h4070c  a_data: 'h4e083aa9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h1a6e9  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4052.122735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test chip_padctrl_attributes has 1 failures.

    • 0.chip_padctrl_attributes.83303076072390052401919556852653089419401262903815549117293412936883413911671
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.