572e2c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 21.000s | 0 | 1 | 0.00 | |
| V1 | smoke | aes_smoke | 46.000s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | aes_csr_hw_reset | 26.000s | 0 | 1 | 0.00 | |
| V1 | csr_rw | aes_csr_rw | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | aes_csr_bit_bash | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | aes_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 21.000s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 21.000s | 0 | 1 | 0.00 | |
| aes_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| V1 | TOTAL | 0 | 7 | 0.00 | |||
| V2 | algorithm | aes_smoke | 46.000s | 0 | 1 | 0.00 | |
| aes_config_error | 25.000s | 0 | 1 | 0.00 | |||
| aes_stress | 38.000s | 0 | 1 | 0.00 | |||
| V2 | key_length | aes_smoke | 46.000s | 0 | 1 | 0.00 | |
| aes_config_error | 25.000s | 0 | 1 | 0.00 | |||
| aes_stress | 38.000s | 0 | 1 | 0.00 | |||
| V2 | back2back | aes_stress | 38.000s | 0 | 1 | 0.00 | |
| aes_b2b | 20.000s | 0 | 1 | 0.00 | |||
| V2 | backpressure | aes_stress | 38.000s | 0 | 1 | 0.00 | |
| V2 | multi_message | aes_smoke | 46.000s | 0 | 1 | 0.00 | |
| aes_config_error | 25.000s | 0 | 1 | 0.00 | |||
| aes_stress | 38.000s | 0 | 1 | 0.00 | |||
| aes_alert_reset | 29.000s | 0 | 1 | 0.00 | |||
| V2 | failure_test | aes_man_cfg_err | 2.000s | 101.877us | 1 | 1 | 100.00 |
| aes_config_error | 25.000s | 0 | 1 | 0.00 | |||
| aes_alert_reset | 29.000s | 0 | 1 | 0.00 | |||
| V2 | trigger_clear_test | aes_clear | 29.000s | 0 | 1 | 0.00 | |
| V2 | nist_test_vectors | aes_nist_vectors | 30.000s | 0 | 1 | 0.00 | |
| V2 | reset_recovery | aes_alert_reset | 29.000s | 0 | 1 | 0.00 | |
| V2 | stress | aes_stress | 38.000s | 0 | 1 | 0.00 | |
| V2 | sideload | aes_stress | 38.000s | 0 | 1 | 0.00 | |
| aes_sideload | 33.000s | 0 | 1 | 0.00 | |||
| V2 | deinitialization | aes_deinit | 34.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | aes_stress_all | 37.000s | 0 | 1 | 0.00 | |
| V2 | alert_test | aes_alert_test | 42.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 17.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | aes_tl_errors | 17.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 26.000s | 0 | 1 | 0.00 | |
| aes_csr_rw | 21.000s | 0 | 1 | 0.00 | |||
| aes_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| aes_same_csr_outstanding | 2.000s | 325.293us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 26.000s | 0 | 1 | 0.00 | |
| aes_csr_rw | 21.000s | 0 | 1 | 0.00 | |||
| aes_csr_aliasing | 29.000s | 0 | 1 | 0.00 | |||
| aes_same_csr_outstanding | 2.000s | 325.293us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 2 | 13 | 15.38 | |||
| V2S | reseeding | aes_reseed | 29.000s | 0 | 1 | 0.00 | |
| V2S | fault_inject | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 18.000s | 0 | 1 | 0.00 | |||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 1.000s | 90.803us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 1.000s | 90.803us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 1.000s | 90.803us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 1.000s | 90.803us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 22.000s | 0 | 1 | 0.00 | |
| V2S | tl_intg_err | aes_sec_cm | 21.000s | 0 | 1 | 0.00 | |
| aes_tl_intg_err | 29.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 1.000s | 90.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 46.000s | 0 | 1 | 0.00 | |
| aes_stress | 38.000s | 0 | 1 | 0.00 | |||
| aes_alert_reset | 29.000s | 0 | 1 | 0.00 | |||
| aes_core_fi | 34.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 1.000s | 90.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 29.000s | 0 | 1 | 0.00 | |
| aes_stress | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_key_sideload | aes_stress | 38.000s | 0 | 1 | 0.00 | |
| aes_sideload | 33.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_key_sec_wipe | aes_readability | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 38.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_key_masking | aes_stress | 38.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_fsm_redun | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 18.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 42.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 18.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 18.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 42.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_ctrl_sparse | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 18.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 42.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 18.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 42.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 18.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 42.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 42.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 29.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 18.000s | 0 | 1 | 0.00 | |||
| V2S | TOTAL | 1 | 11 | 9.09 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 8.000s | 334.220us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 3 | 32 | 9.38 |
Job returned non-zero exit code has 28 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.57180587694092712984087745018306337684070860174154788440286397102223403434612
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_wake_up/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 16:12:16 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.109463538096485253023929041711322206229475228507930133393419116803840888297731
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_nist_vectors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 16:12:25 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_deinit has 1 failures.
0.aes_deinit.109723933269014848205940417988747361749563666190858078431465909254618851565283
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 16:12:31 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_readability has 1 failures.
0.aes_readability.35025438425060756221980388921295123092637641516390247472367197907754591552357
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 16:12:27 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_smoke has 1 failures.
0.aes_smoke.56732225324376447406059076510832135217222036758549401601206368395436714250481
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 16:12:46 UTC (total: 00:00:46)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 23 more tests.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
0.aes_stress_all_with_rand_reset.115022762754649017501979610068036527234327807117212885463907844371764076702044
Line 878, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 334220387 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 334220387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---