572e2c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 0.800s | 742.594us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.100s | 1.068ms | 1 | 1 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 0.690s | 373.333us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 2.500s | 7.144ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 0.970s | 574.770us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.250s | 538.743us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 0.690s | 373.333us | 1 | 1 | 100.00 |
| aon_timer_csr_aliasing | 0.970s | 574.770us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 22.136s | 0 | 1 | 0.00 | |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 0.980s | 339.107us | 1 | 1 | 100.00 |
| V1 | TOTAL | 7 | 8 | 87.50 | |||
| V2 | prescaler | aon_timer_prescaler | 1.100s | 553.351us | 1 | 1 | 100.00 |
| V2 | jump | aon_timer_jump | 0.720s | 592.640us | 1 | 1 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 33.600s | 29.415ms | 1 | 1 | 100.00 |
| V2 | alert_test | aon_timer_alert_test | 0.580s | 424.190us | 1 | 1 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 0.760s | 331.279us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 1.520s | 478.158us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 1.520s | 478.158us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.100s | 1.068ms | 1 | 1 | 100.00 |
| aon_timer_csr_rw | 0.690s | 373.333us | 1 | 1 | 100.00 | ||
| aon_timer_csr_aliasing | 0.970s | 574.770us | 1 | 1 | 100.00 | ||
| aon_timer_same_csr_outstanding | 1.350s | 2.479ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.100s | 1.068ms | 1 | 1 | 100.00 |
| aon_timer_csr_rw | 0.690s | 373.333us | 1 | 1 | 100.00 | ||
| aon_timer_csr_aliasing | 0.970s | 574.770us | 1 | 1 | 100.00 | ||
| aon_timer_same_csr_outstanding | 1.350s | 2.479ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 7 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 2.940s | 8.349ms | 1 | 1 | 100.00 |
| aon_timer_tl_intg_err | 3.040s | 3.964ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 3.040s | 3.964ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | max_threshold | aon_timer_smoke_max_thold | 0.640s | 496.064us | 1 | 1 | 100.00 |
| V3 | min_threshold | aon_timer_smoke_min_thold | 0.900s | 592.850us | 1 | 1 | 100.00 |
| V3 | wkup_count_hi_cdc | aon_timer_wkup_count_cdc_hi | 7.210s | 4.194ms | 1 | 1 | 100.00 |
| V3 | custom_intr | aon_timer_custom_intr | 0.670s | 524.038us | 1 | 1 | 100.00 |
| V3 | alternating_on_off | aon_timer_alternating_enable_on_off | 9.070s | 4.123ms | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 13.870s | 3.567ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 6 | 6 | 100.00 | |||
| TOTAL | 22 | 23 | 95.65 |
Job returned non-zero exit code has 1 failures:
0.aon_timer_mem_walk.108014460413892656179371300894698102786883520130635119266011101661496968047095
Log /nightly/current_run/scratch/master/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255