572e2c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 0.810s | 16.696us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | edn_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | edn_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | edn_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0 | 1 | 0.00 | ||
| edn_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | TOTAL | 1 | 6 | 16.67 | |||
| V2 | firmware | edn_genbits | 1.860s | 175.832us | 1 | 1 | 100.00 |
| V2 | csrng_commands | edn_genbits | 1.860s | 175.832us | 1 | 1 | 100.00 |
| V2 | genbits | edn_genbits | 1.860s | 175.832us | 1 | 1 | 100.00 |
| V2 | interrupts | edn_intr | 0.790s | 57.227us | 1 | 1 | 100.00 |
| V2 | alerts | edn_alert | 0.940s | 89.099us | 1 | 1 | 100.00 |
| V2 | errs | edn_err | 0.880s | 19.371us | 1 | 1 | 100.00 |
| V2 | disable | edn_disable | 0.750s | 39.918us | 1 | 1 | 100.00 |
| edn_disable_auto_req_mode | 0.830s | 184.822us | 1 | 1 | 100.00 | ||
| V2 | stress_all | edn_stress_all | 2.120s | 145.079us | 1 | 1 | 100.00 |
| V2 | intr_test | edn_intr_test | 0 | 1 | 0.00 | ||
| V2 | alert_test | edn_alert_test | 0.740s | 179.195us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | edn_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0 | 1 | 0.00 | ||
| edn_csr_rw | 0 | 1 | 0.00 | ||||
| edn_csr_aliasing | 0 | 1 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0 | 1 | 0.00 | ||
| edn_csr_rw | 0 | 1 | 0.00 | ||||
| edn_csr_aliasing | 0 | 1 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 8 | 11 | 72.73 | |||
| V2S | tl_intg_err | edn_sec_cm | 15.962s | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_config_regwen | edn_regwen | 0.740s | 46.935us | 1 | 1 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 0.940s | 89.099us | 1 | 1 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 15.962s | 0 | 1 | 0.00 | |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 15.962s | 0 | 1 | 0.00 | |
| V2S | sec_cm_fifo_ctr_redun | edn_sec_cm | 15.962s | 0 | 1 | 0.00 | |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 15.962s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 0.940s | 89.099us | 1 | 1 | 100.00 |
| edn_sec_cm | 15.962s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 0.940s | 89.099us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 3 | 33.33 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 10 | 21 | 47.62 |
Job killed most likely because its dependent job failed. has 9 failures:
Test edn_tl_errors has 1 failures.
Test edn_tl_intg_err has 1 failures.
Test edn_intr_test has 1 failures.
Test edn_csr_hw_reset has 1 failures.
Test edn_csr_rw has 1 failures.
... and 4 more tests.
Job timed out after * minutes has 2 failures:
Test cover_reg_top has 1 failures.
cover_reg_top
Log /nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/build.log
Job timed out after 60 minutes
Test edn_stress_all_with_rand_reset has 1 failures.
0.edn_stress_all_with_rand_reset.8782438449129730028949784136695776368966563508092213504557817471974035411426
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
Job returned non-zero exit code has 1 failures:
0.edn_sec_cm.59859102918628089440940866258057693687028299144254293746294907588066353836643
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_sec_cm/latest/run.log
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255