HMAC Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: 572e2c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	0.900s	75.172us	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.730s	56.645us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.710s	85.292us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	3.470s	422.634us	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.730s	584.777us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	1.040s	92.966us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.710s	85.292us	1	1	100.00
		hmac_csr_aliasing	5.730s	584.777us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	19.840s	8.263ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	4.550s	481.647us	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	7.410s	331.186us	1	1	100.00
		hmac_test_sha384_vectors	18.770s	1.115ms	1	1	100.00
		hmac_test_sha512_vectors	18.500s	268.031us	1	1	100.00
		hmac_test_hmac256_vectors	5.370s	741.065us	1	1	100.00
		hmac_test_hmac384_vectors	9.500s	578.728us	1	1	100.00
		hmac_test_hmac512_vectors	10.030s	1.179ms	1	1	100.00
V2	burst_wr	hmac_burst_wr	18.710s	1.499ms	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	13.084m	25.828ms	1	1	100.00
V2	error	hmac_error	10.450s	2.359ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	24.462s		0	1	0.00
V2	save_and_restore	hmac_smoke	0.900s	75.172us	1	1	100.00
		hmac_long_msg	19.840s	8.263ms	1	1	100.00
		hmac_back_pressure	4.550s	481.647us	1	1	100.00
		hmac_datapath_stress	13.084m	25.828ms	1	1	100.00
		hmac_burst_wr	18.710s	1.499ms	1	1	100.00
		hmac_stress_all	12.158m	12.553ms	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	0.900s	75.172us	1	1	100.00
		hmac_long_msg	19.840s	8.263ms	1	1	100.00
		hmac_back_pressure	4.550s	481.647us	1	1	100.00
		hmac_datapath_stress	13.084m	25.828ms	1	1	100.00
		hmac_wipe_secret	24.462s		0	1	0.00
		hmac_test_sha256_vectors	7.410s	331.186us	1	1	100.00
		hmac_test_sha384_vectors	18.770s	1.115ms	1	1	100.00
		hmac_test_sha512_vectors	18.500s	268.031us	1	1	100.00
		hmac_test_hmac256_vectors	5.370s	741.065us	1	1	100.00
		hmac_test_hmac384_vectors	9.500s	578.728us	1	1	100.00
		hmac_test_hmac512_vectors	10.030s	1.179ms	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	0.900s	75.172us	1	1	100.00
		hmac_long_msg	19.840s	8.263ms	1	1	100.00
		hmac_back_pressure	4.550s	481.647us	1	1	100.00
		hmac_datapath_stress	13.084m	25.828ms	1	1	100.00
		hmac_burst_wr	18.710s	1.499ms	1	1	100.00
		hmac_error	10.450s	2.359ms	1	1	100.00
		hmac_wipe_secret	24.462s		0	1	0.00
		hmac_test_sha256_vectors	7.410s	331.186us	1	1	100.00
		hmac_test_sha384_vectors	18.770s	1.115ms	1	1	100.00
		hmac_test_sha512_vectors	18.500s	268.031us	1	1	100.00
		hmac_test_hmac256_vectors	5.370s	741.065us	1	1	100.00
		hmac_test_hmac384_vectors	9.500s	578.728us	1	1	100.00
		hmac_test_hmac512_vectors	10.030s	1.179ms	1	1	100.00
		hmac_stress_all	12.158m	12.553ms	1	1	100.00
V2	stress_all	hmac_stress_all	12.158m	12.553ms	1	1	100.00
V2	alert_test	hmac_alert_test	0.580s	13.039us	1	1	100.00
V2	intr_test	hmac_intr_test	0.550s	13.291us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	1.090s	48.871us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	1.090s	48.871us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.730s	56.645us	1	1	100.00
		hmac_csr_rw	0.710s	85.292us	1	1	100.00
		hmac_csr_aliasing	5.730s	584.777us	1	1	100.00
		hmac_same_csr_outstanding	1.540s	176.611us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.730s	56.645us	1	1	100.00
		hmac_csr_rw	0.710s	85.292us	1	1	100.00
		hmac_csr_aliasing	5.730s	584.777us	1	1	100.00
		hmac_same_csr_outstanding	1.540s	176.611us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	tl_intg_err	hmac_sec_cm	0.830s	190.967us	1	1	100.00
		hmac_tl_intg_err	2.000s	934.720us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.000s	934.720us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	0.900s	75.172us	1	1	100.00
V3	stress_reset	hmac_stress_reset	15.582s		0	1	0.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	52.680s	20.096ms	1	1	100.00
V3		TOTAL			1	2	50.00
	Unmapped tests	hmac_directed	1.490s	54.631us	1	1	100.00
		TOTAL			26	28	92.86

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test hmac_stress_reset has 1 failures.

    • 0.hmac_stress_reset.85099268001804957185436817561689263282304687176312353342821619785756151297972
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_stress_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:08 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test hmac_wipe_secret has 1 failures.

    • 0.hmac_wipe_secret.18198759461807433921719944271249979444785678827772157233880182200645685973014
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:08 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255