KEYMGR Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: 572e2c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.000s	230.580us	1	1	100.00
V1	random	keymgr_random	2.740s	576.083us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.820s	18.918us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	20.323s		0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.970s	1.369ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.050s	960.602us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.120s	89.162us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	20.323s		0	1	0.00
		keymgr_csr_aliasing	3.050s	960.602us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	1.970s	35.299us	1	1	100.00
V2	sideload	keymgr_sideload	1.760s	150.780us	1	1	100.00
		keymgr_sideload_kmac	2.450s	109.047us	1	1	100.00
		keymgr_sideload_aes	1.720s	226.949us	1	1	100.00
		keymgr_sideload_otbn	28.130s	1.530ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.510s	174.661us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.980s	600.323us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.440s	83.909us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.060s	96.704us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.620s	119.341us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.070s	339.679us	1	1	100.00
V2	stress_all	keymgr_stress_all	33.360s	6.589ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.640s	10.564us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.640s	97.106us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.680s	80.288us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.680s	80.288us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.820s	18.918us	1	1	100.00
		keymgr_csr_rw	20.323s		0	1	0.00
		keymgr_csr_aliasing	3.050s	960.602us	1	1	100.00
		keymgr_same_csr_outstanding	1.760s	71.466us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.820s	18.918us	1	1	100.00
		keymgr_csr_rw	20.323s		0	1	0.00
		keymgr_csr_aliasing	3.050s	960.602us	1	1	100.00
		keymgr_same_csr_outstanding	1.760s	71.466us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
		keymgr_tl_intg_err	3.840s	288.450us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	1.590s	183.686us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	1.590s	183.686us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	1.590s	183.686us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	1.590s	183.686us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.460s	373.440us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.840s	288.450us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	1.590s	183.686us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.970s	35.299us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.740s	576.083us	1	1	100.00
		keymgr_csr_rw	20.323s		0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.740s	576.083us	1	1	100.00
		keymgr_csr_rw	20.323s		0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.740s	576.083us	1	1	100.00
		keymgr_csr_rw	20.323s		0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.980s	600.323us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.620s	119.341us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.620s	119.341us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.740s	576.083us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.960s	160.221us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.250s	114.929us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.980s	600.323us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.250s	114.929us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.250s	114.929us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.250s	114.929us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.680s	3.787ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.250s	114.929us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.430s	1.573ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.35731291838821199404438981954829240888525025351755009173261022751100934073480
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:07 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255