KMAC/MASKED Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: 572e2c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	21.150s	1.866ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.880s	26.358us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.940s	49.932us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.420s	2.023ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.200s	395.105us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.140s	1.315ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.940s	49.932us	1	1	100.00
		kmac_csr_aliasing	6.200s	395.105us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.660s	21.287us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.000s	129.603us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	43.876m	266.719ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.970s	289.472us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.190s	5.053ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.820s	1.170ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.900s	9.778ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.595m	676.765ms	1	1	100.00
		kmac_test_vectors_shake_128	2.544m	10.411ms	1	1	100.00
		kmac_test_vectors_shake_256	1.671m	13.794ms	1	1	100.00
		kmac_test_vectors_kmac	2.050s	45.718us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.940s	74.717us	1	1	100.00
V2	sideload	kmac_sideload	4.622m	256.186ms	1	1	100.00
V2	app	kmac_app	1.645m	26.785ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	40.280s	4.213ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	31.700s	7.808ms	1	1	100.00
V2	error	kmac_error	4.106m	55.696ms	1	1	100.00
V2	key_error	kmac_key_error	7.020s	5.769ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid			0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	11.630s	2.225ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	25.500s	1.630ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	18.120s		0	1	0.00
V2	lc_escalation	kmac_lc_escalation	1.230s	53.194us	1	1	100.00
V2	stress_all	kmac_stress_all	53.310s	3.985ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.740s	19.740us	1	1	100.00
V2	alert_test	kmac_alert_test	0.800s	19.413us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.980s	1.366ms	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.980s	1.366ms	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.880s	26.358us	1	1	100.00
		kmac_csr_rw	0.940s	49.932us	1	1	100.00
		kmac_csr_aliasing	6.200s	395.105us	1	1	100.00
		kmac_same_csr_outstanding	1.160s	28.345us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.880s	26.358us	1	1	100.00
		kmac_csr_rw	0.940s	49.932us	1	1	100.00
		kmac_csr_aliasing	6.200s	395.105us	1	1	100.00
		kmac_same_csr_outstanding	1.160s	28.345us	1	1	100.00
V2		TOTAL			24	26	92.31
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.210s	64.111us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.210s	64.111us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.210s	64.111us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.210s	64.111us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.910s	103.308us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	34.220s	8.559ms	1	1	100.00
		kmac_tl_intg_err	1.840s	432.637us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.840s	432.637us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.230s	53.194us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	21.150s	1.866ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.622m	256.186ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.210s	64.111us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.220s	8.559ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.220s	8.559ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.220s	8.559ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	21.150s	1.866ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.230s	53.194us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.220s	8.559ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.685m	14.017ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	21.150s	1.866ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.584m	29.866ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.84032833995537076202693083626421617582796408178463264192982490109254789181101
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        Job timed out after 60 minutes
      

• Job returned non-zero exit code has 1 failures:

  • Test kmac_entropy_ready_error has 1 failures.

    • 0.kmac_entropy_ready_error.84125477050909454756370065465168288822332121344043614760026825819781418390609
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:19 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255