572e2c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 32.360s | 968.746us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0.800s | 50.619us | 1 | 1 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 0.870s | 91.148us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 16.273s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | kmac_csr_aliasing | 2.790s | 300.202us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 1.290s | 26.243us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0.870s | 91.148us | 1 | 1 | 100.00 |
| kmac_csr_aliasing | 2.790s | 300.202us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.670s | 24.270us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.110s | 71.305us | 1 | 1 | 100.00 |
| V1 | TOTAL | 7 | 8 | 87.50 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 4.172m | 29.640ms | 1 | 1 | 100.00 |
| V2 | burst_write | kmac_burst_write | 23.831s | 0 | 1 | 0.00 | |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 23.850s | 2.725ms | 1 | 1 | 100.00 |
| kmac_test_vectors_sha3_256 | 21.480s | 595.948us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 14.470s | 1.631ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 8.546m | 9.711ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_128 | 2.074m | 10.083ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_256 | 4.170m | 22.476ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac | 1.810s | 336.918us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 1.880s | 222.984us | 1 | 1 | 100.00 | ||
| V2 | sideload | kmac_sideload | 58.440s | 1.164ms | 1 | 1 | 100.00 |
| V2 | app | kmac_app | 59.250s | 12.527ms | 1 | 1 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 27.096s | 0 | 1 | 0.00 | |
| V2 | entropy_refresh | kmac_entropy_refresh | 3.825m | 39.457ms | 1 | 1 | 100.00 |
| V2 | error | kmac_error | 1.690m | 4.471ms | 1 | 1 | 100.00 |
| V2 | key_error | kmac_key_error | 26.174s | 0 | 1 | 0.00 | |
| V2 | sideload_invalid | kmac_sideload_invalid | 29.440s | 10.059ms | 0 | 1 | 0.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 15.730s | 4.313ms | 1 | 1 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 18.233s | 0 | 1 | 0.00 | |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 28.080s | 6.941ms | 1 | 1 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 0.970s | 85.893us | 1 | 1 | 100.00 |
| V2 | stress_all | kmac_stress_all | 1.898m | 13.671ms | 1 | 1 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0.650s | 15.525us | 1 | 1 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.680s | 18.431us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 1.430s | 115.359us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 1.430s | 115.359us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0.800s | 50.619us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.870s | 91.148us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 2.790s | 300.202us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0.800s | 50.619us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.870s | 91.148us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 2.790s | 300.202us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 20 | 26 | 76.92 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.310s | 99.618us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.310s | 99.618us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.310s | 99.618us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.310s | 99.618us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 2.100s | 246.500us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 19.740s | 30.242ms | 1 | 1 | 100.00 |
| kmac_tl_intg_err | 2.980s | 509.740us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 2.980s | 509.740us | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0.970s | 85.893us | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 32.360s | 968.746us | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 58.440s | 1.164ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.310s | 99.618us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 19.740s | 30.242ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 19.740s | 30.242ms | 1 | 1 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 19.740s | 30.242ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 32.360s | 968.746us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0.970s | 85.893us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 19.740s | 30.242ms | 1 | 1 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 11.270s | 261.433us | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 32.360s | 968.746us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 15.060s | 1.620ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 33 | 40 | 82.50 |
Job returned non-zero exit code has 5 failures:
Test kmac_burst_write has 1 failures.
0.kmac_burst_write.98042566880860501161274445319770487514896037710581031226510139932346873298213
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:10 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_app_with_partial_data has 1 failures.
0.kmac_app_with_partial_data.72032082259394187951205095376161872667242872043497608222537455618587155437435
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:10 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_key_error has 1 failures.
0.kmac_key_error.36098143144503697350873736294863322299493203486873998166133254951648980063321
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_key_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:10 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_entropy_mode_error has 1 failures.
0.kmac_entropy_mode_error.82581730299422954987340267903208539305331041027626448531848968465883263568329
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:10 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_csr_bit_bash has 1 failures.
0.kmac_csr_bit_bash.89362124654334545348958731131203320992676153419446371027327685367920040215646
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:10 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
0.kmac_sideload_invalid.13776179439396557555761442553522361266050729333388718021654724279655251457823
Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10059001233 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2e2d6000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10059001233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
0.kmac_same_csr_outstanding.12979956315741724496964446908130707058380748244190399047560436671025226643713
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest/run.log
Job timed out after 60 minutes