572e2c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| Unmapped tests | prim_prince_test | 0 | 1 | 0.00 | |||
| TOTAL | 0 | 1 | 0.00 |
Job returned non-zero exit code has 1 failures:
default
Log /nightly/current_run/scratch/master/prim_prince-sim-vcs/default/build.log
recompiling module prim_prince_tb
All of 29 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 6.959 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Job killed most likely because its dependent job failed. has 1 failures: