PRIM_PRINCE Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: 572e2c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
	Unmapped tests	prim_prince_test			0	1	0.00
		TOTAL			0	1	0.00

Failure Buckets

• Job returned non-zero exit code has 1 failures:

  • Test default has 1 failures.

    • default
      Log /nightly/current_run/scratch/master/prim_prince-sim-vcs/default/build.log

        recompiling module prim_prince_tb
        All of 29 modules done
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        CPU time: 6.959 seconds to compile
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
      

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test prim_prince_test has 1 failures.
    • 0.prim_prince_test.70666397069420055342025610871842983609562821345168386419401295683458846582257
      Log /nightly/current_run/scratch/master/prim_prince-sim-vcs/0.prim_prince_test/latest/run.log