ROM_CTRL/32KB Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: 572e2c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	3.390s	699.196us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	4.210s	941.466us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.160s	147.031us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.630s	633.831us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	3.370s	537.860us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	3.670s	309.036us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.160s	147.031us	1	1	100.00
		rom_ctrl_csr_aliasing	3.370s	537.860us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.470s	294.829us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.290s	127.974us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	4.650s	182.458us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	10.030s	1.657ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.330s	307.110us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	2.980s	384.607us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.160s	168.360us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.160s	168.360us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	4.210s	941.466us	1	1	100.00
		rom_ctrl_csr_rw	3.160s	147.031us	1	1	100.00
		rom_ctrl_csr_aliasing	3.370s	537.860us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.410s	1.166ms	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	4.210s	941.466us	1	1	100.00
		rom_ctrl_csr_rw	3.160s	147.031us	1	1	100.00
		rom_ctrl_csr_aliasing	3.370s	537.860us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.410s	1.166ms	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	15.770s	6.770ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.700m	849.845us	0	1	0.00
		rom_ctrl_tl_intg_err	24.164s		0	1	0.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.700m	849.845us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.700m	849.845us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.700m	849.845us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.700m	849.845us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	3.390s	699.196us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	3.390s	699.196us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	3.390s	699.196us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.164s		0	1	0.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
		rom_ctrl_kmac_err_chk	7.330s	307.110us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	50.220s	2.370ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	15.770s	6.770ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.700m	849.845us	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	16.340s	3.020ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	19	89.47

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.76928268936842220416849345823668389240004631336627974734854787703667782882131
      Line 190, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 63876088ps failed at 63876088ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 63876088ps failed at 63876088ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Job returned non-zero exit code has 1 failures:

  • Test rom_ctrl_tl_intg_err has 1 failures.

    • 0.rom_ctrl_tl_intg_err.19991754789600031323831487041099724642108522229081444691243650188549732309687
      Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest/run.log

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        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255