SPI_DEVICE/1R1W Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: `572e2c3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	22.300s	31.194ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.950s	124.927us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	0.980s	125.696us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	7.780s	182.137us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.030s	313.731us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.640s	117.014us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	0.980s	125.696us	1	1	100.00
		spi_device_csr_aliasing	5.030s	313.731us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	27.393us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.270s	223.129us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.690s	33.141us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.640s	6.797us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	20.775s		0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.030s	191.894us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.030s	191.894us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.130s	3.447ms	1	1	100.00
		spi_device_tpm_sts_read	24.415s		0	1	0.00
V2	tpm_fully_random_case	spi_device_tpm_all	6.990s	3.384ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.590s	584.637us	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.370s	2.757ms	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.370s	2.757ms	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	1.710s	151.013us	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	1.710s	151.013us	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	1.710s	151.013us	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	1.710s	151.013us	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	1.710s	151.013us	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.940s	5.103ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.010s	2.691ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.010s	2.691ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.010s	2.691ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.850s	3.814ms	1	1	100.00
		spi_device_read_buffer_direct	2.520s	399.696us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.010s	2.691ms	1	1	100.00
		spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.099m	14.248ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.470s	172.480us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.470s	172.480us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	22.300s	31.194ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.539m	27.881ms	1	1	100.00
V2	stress_all	spi_device_stress_all	4.238m	151.090ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.680s	16.871us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.670s	17.160us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	24.155s		0	1	0.00
V2	tl_d_illegal_access	spi_device_tl_errors	24.155s		0	1	0.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.950s	124.927us	1	1	100.00
		spi_device_csr_rw	0.980s	125.696us	1	1	100.00
		spi_device_csr_aliasing	5.030s	313.731us	1	1	100.00
		spi_device_same_csr_outstanding	1.390s	70.253us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.950s	124.927us	1	1	100.00
		spi_device_csr_rw	0.980s	125.696us	1	1	100.00
		spi_device_csr_aliasing	5.030s	313.731us	1	1	100.00
		spi_device_same_csr_outstanding	1.390s	70.253us	1	1	100.00
V2		TOTAL			18	22	81.82
V2S	tl_intg_err	spi_device_sec_cm	0.950s	249.900us	1	1	100.00
		spi_device_tl_intg_err			0	1	0.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err			0	1	0.00
V2S		TOTAL			1	2	50.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	28.470s	7.000ms	1	1	100.00
		TOTAL			28	33	84.85

Failure Buckets

Job returned non-zero exit code has 3 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.78587488005154280671152430095414940021902211460217781389507682972827901986330
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  Chronologic VCS simulator copyright 1991-2023
  Contains Synopsys proprietary information.
  Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:14 2025
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.

  Please contact VCS Customer Support at 1-800-VERILOG for more information.

  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255

Test spi_device_tpm_sts_read has 1 failures.

0.spi_device_tpm_sts_read.113049355045291912215792915254728020392484228117069720007553829359696722888820
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest/run.log

  Chronologic VCS simulator copyright 1991-2023
  Contains Synopsys proprietary information.
  Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:15 2025
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.

  Please contact VCS Customer Support at 1-800-VERILOG for more information.

  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255

Test spi_device_tl_errors has 1 failures.

0.spi_device_tl_errors.96145626882477703091022675091060383343959882824728027101615381147619063120483
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest/run.log

  Chronologic VCS simulator copyright 1991-2023
  Contains Synopsys proprietary information.
  Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:14 2025
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.

  Please contact VCS Customer Support at 1-800-VERILOG for more information.

  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

Test spi_device_mem_parity has 1 failures.

0.spi_device_mem_parity.71951299215216987647178393046301375332335350795218638702307011489065987817657
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4130605 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[9])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4130605 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4130605 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

Job timed out after * minutes has 1 failures:
- Test spi_device_tl_intg_err has 1 failures.
  - 0.spi_device_tl_intg_err.29057284634332981111079467592390095613769767968246099707029818942030376131620
    Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest/run.log
```
  Job timed out after 60 minutes
```