SRAM_CTRL/MAIN Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: 572e2c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	15.770s	14.184ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.630s	14.975us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.630s	53.976us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.560s	125.331us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.680s	22.001us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.330s	352.516us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.630s	53.976us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	22.001us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.247m	10.497ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	53.850s	10.530ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.013m	83.261ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.200m	4.437ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	20.212m	80.828ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.245m	6.987ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	8.920s	3.946ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.128m	21.703ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.340s	403.378us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.068m	7.314ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	17.050s	730.786us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	14.580s	2.898ms	1	1	100.00
		sram_ctrl_throughput_w_readback	17.350s	1.050ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.312m	1.079ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.260s	700.481us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	59.543m	72.424ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.630s	14.239us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.580s	101.241us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.580s	101.241us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.630s	14.975us	1	1	100.00
		sram_ctrl_csr_rw	0.630s	53.976us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	22.001us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	30.389us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.630s	14.975us	1	1	100.00
		sram_ctrl_csr_rw	0.630s	53.976us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	22.001us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	30.389us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	27.240s	7.517ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.610s	1.900us	0	1	0.00
		sram_ctrl_tl_intg_err	1.620s	633.526us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.610s	1.900us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.620s	633.526us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.312m	1.079ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.312m	1.079ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.630s	53.976us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.128m	21.703ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.128m	21.703ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.128m	21.703ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	8.920s	3.946ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.920s	2.700ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	27.240s	7.517ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.250s	2.628ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	15.770s	14.184ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	15.770s	14.184ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.128m	21.703ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.610s	1.900us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	8.920s	3.946ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.610s	1.900us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.610s	1.900us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	15.770s	14.184ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.610s	1.900us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	53.870s	13.273ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.16261975562907862993887589308808626571546734644171632353572780418985404568371
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2627519192 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xb) != exp (0x44)
        UVM_INFO @ 2627519192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.62210518202906929272608050875682816969261617049663121785703665985778152371007
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   1899903 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1899903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---