572e2c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 4.780s | 126.797us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.630s | 25.146us | 1 | 1 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.610s | 65.791us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.110s | 89.215us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 18.350s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 0.710s | 96.279us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.610s | 65.791us | 1 | 1 | 100.00 |
| sram_ctrl_csr_aliasing | 18.350s | 0 | 1 | 0.00 | |||
| V1 | mem_walk | sram_ctrl_mem_walk | 3.710s | 188.237us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 3.570s | 407.495us | 1 | 1 | 100.00 |
| V1 | TOTAL | 7 | 8 | 87.50 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 14.120m | 25.064ms | 1 | 1 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 4.074m | 17.374ms | 1 | 1 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 15.730s | 370.281us | 1 | 1 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 26.247s | 0 | 1 | 0.00 | |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 7.690s | 2.751ms | 1 | 1 | 100.00 |
| V2 | executable | sram_ctrl_executable | 3.501m | 20.996ms | 1 | 1 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 15.180s | 564.042us | 1 | 1 | 100.00 |
| sram_ctrl_partial_access_b2b | 4.521m | 5.225ms | 1 | 1 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 16.510s | 193.909us | 1 | 1 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 18.310s | 791.082us | 1 | 1 | 100.00 | ||
| sram_ctrl_throughput_w_readback | 27.600s | 259.613us | 1 | 1 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 5.699m | 14.365ms | 1 | 1 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.690s | 82.138us | 1 | 1 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 10.762m | 19.583ms | 1 | 1 | 100.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.620s | 15.724us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 1.790s | 117.508us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 1.790s | 117.508us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.630s | 25.146us | 1 | 1 | 100.00 |
| sram_ctrl_csr_rw | 0.610s | 65.791us | 1 | 1 | 100.00 | ||
| sram_ctrl_csr_aliasing | 18.350s | 0 | 1 | 0.00 | |||
| sram_ctrl_same_csr_outstanding | 0.620s | 26.175us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.630s | 25.146us | 1 | 1 | 100.00 |
| sram_ctrl_csr_rw | 0.610s | 65.791us | 1 | 1 | 100.00 | ||
| sram_ctrl_csr_aliasing | 18.350s | 0 | 1 | 0.00 | |||
| sram_ctrl_same_csr_outstanding | 0.620s | 26.175us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 16 | 17 | 94.12 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 24.867s | 0 | 1 | 0.00 | |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0.670s | 4.181us | 0 | 1 | 0.00 |
| sram_ctrl_tl_intg_err | 1.160s | 83.511us | 1 | 1 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0.670s | 4.181us | 0 | 1 | 0.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 1.160s | 83.511us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 5.699m | 14.365ms | 1 | 1 | 100.00 |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 5.699m | 14.365ms | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.610s | 65.791us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 3.501m | 20.996ms | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 3.501m | 20.996ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 3.501m | 20.996ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 7.690s | 2.751ms | 1 | 1 | 100.00 |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 0.830s | 327.151us | 0 | 1 | 0.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 24.867s | 0 | 1 | 0.00 | |
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 0.810s | 24.500us | 0 | 1 | 0.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 4.780s | 126.797us | 1 | 1 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 4.780s | 126.797us | 1 | 1 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 3.501m | 20.996ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0.670s | 4.181us | 0 | 1 | 0.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 7.690s | 2.751ms | 1 | 1 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0.670s | 4.181us | 0 | 1 | 0.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0.670s | 4.181us | 0 | 1 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 4.780s | 126.797us | 1 | 1 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0.670s | 4.181us | 0 | 1 | 0.00 |
| V2S | TOTAL | 1 | 5 | 20.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 1.820m | 9.304ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 25 | 31 | 80.65 |
Job returned non-zero exit code has 3 failures:
Test sram_ctrl_access_during_key_req has 1 failures.
0.sram_ctrl_access_during_key_req.8361658706278018711303760358083536143193503103154657227368192279563288639970
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:09 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
0.sram_ctrl_passthru_mem_tl_intg_err.4733643821776769225955913652941343183798707432897270824465069474732991379079
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:09 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test sram_ctrl_csr_aliasing has 1 failures.
0.sram_ctrl_csr_aliasing.17872550562240843259326427800835718787370551458886287733665483126123481647559
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 16:09 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
0.sram_ctrl_readback_err.33664614703882599359694005849180461472854499739800905236656595499906149950009
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 24500324 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x10)
UVM_INFO @ 24500324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid' has 1 failures:
0.sram_ctrl_mubi_enc_err.19581635169232523603209480054209479970560480578529608115911970870585774712190
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 327150920 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 327150920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
0.sram_ctrl_sec_cm.46505799472681173575212354776813068129733244461852010236896662292777756572975
Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 4180515 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4180515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---