UART Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: 572e2c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	20.320s		0	1	0.00
V1	csr_hw_reset	uart_csr_hw_reset	19.695s		0	1	0.00
V1	csr_rw	uart_csr_rw	0.600s	35.806us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.190s	358.551us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	57.662us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.870s	21.074us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.600s	35.806us	1	1	100.00
		uart_csr_aliasing	0.700s	57.662us	1	1	100.00
V1		TOTAL			4	6	66.67
V2	base_random_seq	uart_tx_rx	27.910s	78.528ms	1	1	100.00
V2	parity	uart_smoke	20.320s		0	1	0.00
		uart_tx_rx	27.910s	78.528ms	1	1	100.00
V2	parity_error	uart_intr	21.270s	32.985ms	1	1	100.00
		uart_rx_parity_err	1.180m	84.262ms	1	1	100.00
V2	watermark	uart_tx_rx	27.910s	78.528ms	1	1	100.00
		uart_intr	21.270s	32.985ms	1	1	100.00
V2	fifo_full	uart_fifo_full	24.320s	29.921ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.930m	101.278ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	14.670s	51.627ms	1	1	100.00
V2	rx_frame_err	uart_intr	21.270s	32.985ms	1	1	100.00
V2	rx_break_err	uart_intr	21.270s	32.985ms	1	1	100.00
V2	rx_timeout	uart_intr	21.270s	32.985ms	1	1	100.00
V2	perf	uart_perf	6.430m	12.672ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.890s	10.195ms	1	1	100.00
V2	line_loopback	uart_loopback	2.890s	10.195ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	5.400s	20.719ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	23.650s	46.430ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.060s	746.611us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.390s	5.156ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.099m	92.310ms	1	1	100.00
V2	stress_all	uart_stress_all	3.431m	227.389ms	0	1	0.00
V2	alert_test	uart_alert_test	0.550s	28.439us	1	1	100.00
V2	intr_test	uart_intr_test	0.580s	51.028us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.510s	82.207us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.510s	82.207us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	19.695s		0	1	0.00
		uart_csr_rw	0.600s	35.806us	1	1	100.00
		uart_csr_aliasing	0.700s	57.662us	1	1	100.00
		uart_same_csr_outstanding	0.630s	21.330us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	19.695s		0	1	0.00
		uart_csr_rw	0.600s	35.806us	1	1	100.00
		uart_csr_aliasing	0.700s	57.662us	1	1	100.00
		uart_same_csr_outstanding	0.630s	21.330us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	0.800s	90.843us	1	1	100.00
		uart_tl_intg_err	1.170s	307.428us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.170s	307.428us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.450s	8.775ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			23	27	85.19

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test uart_smoke has 1 failures.

    • 0.uart_smoke.47981771963367009003853360968166150113227995295190034045493029426346071949660
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_smoke/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:13 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test uart_csr_hw_reset has 1 failures.

    • 0.uart_csr_hw_reset.20641131695845962348906924827629439875285696680483443179192754646095826088570
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_csr_hw_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 16:16 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.93732836916376724508328177218466397280574165969229952392459440930839606388102
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 18268197459 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 18268239126 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 18268364127 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 18268405794 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 18268530795 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.61193896047084263250983585579652312714079835370781313567211974115904458190261
      Line 95, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 225506747641 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 225506766509 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 225506785377 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (91 [0x5b] vs 247 [0xf7]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 225506804245 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 225506823113 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (91 [0x5b] vs 222 [0xde]) reg name: uart_reg_block.rdata