CHIP Simulation Results

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: `572e2c3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	18.313s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	18.313s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	14.846s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	13.931s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	13.151s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.542s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.542s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.542s		0	1	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	14.328s		0	1	0.00
		chip_sw_example_manufacturer	14.218s		0	1	0.00
		chip_sw_example_concurrency	12.845s		0	1	0.00
		chip_sw_uart_smoketest_signed	50.884s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.110s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	7.830s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	7.830s		0	1	0.00
V1	xbar_smoke	xbar_smoke	17.940s	65.887us	1	1	100.00
V1		TOTAL			1	12	8.33
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	16.848s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.435s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.492s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.481s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	10.738s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	11.552s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.014s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.710s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.710s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.127s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	10.174s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	10.131s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	10.131s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.935m	4.991ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.031m	3.658ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	11.476s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.617s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.569s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.442m	19.254ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	32.904s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	32.676s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	32.676s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	30.755s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	30.806s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	30.806s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	30.708s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	19.106s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	30.537s		0	1	0.00
		chip_sw_aes_idle	16.494s		0	1	0.00
		chip_sw_hmac_enc_idle	19.190s		0	1	0.00
		chip_sw_kmac_idle	19.786s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	17.296s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	17.294s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	17.845s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	16.703s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	17.291s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.702s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.963s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	17.081s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	17.406s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	16.691s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	16.695s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.291s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.702s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.963s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	17.081s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	17.406s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	16.691s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	16.695s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	31.975s		0	1	0.00
		chip_sw_aes_enc_jitter_en	27.996s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	19.354s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	20.393s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	19.247s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.621s		0	1	0.00
		chip_sw_clkmgr_jitter	15.828s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	16.608s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	15.583s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	15.753s		0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	16.928s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	16.494s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	16.651s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	15.186s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	15.238s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.266s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	16.704s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	16.701s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	10.280s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	14.097s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	30.806s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	31.024s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	14.097s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.750s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	10.399s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.437s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.524s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	10.397s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	10.280s		0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	11.476s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.798s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	14.271s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.602s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	15.134s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	10.280s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	17.162s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	16.455s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	10.280s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	15.826s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.602s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	15.862s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	16.798s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	16.855s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	15.595s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.099s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	16.244s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	16.455s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.430s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	19.796s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.326s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.070s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.611s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.508s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	19.792s		0	1	0.00
		chip_sw_rom_ctrl_integrity_check	18.864s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	18.529s		0	1	0.00
		chip_prim_tl_access	32.135s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.291s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.702s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.963s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	17.081s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	17.406s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	16.691s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	16.695s		0	1	0.00
		chip_rv_dm_lc_disabled	12.442m	19.254ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	30.224s		0	1	0.00
		chip_sw_aes_enc_jitter_en	27.996s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	15.943s		0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	16.494s		0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	19.245s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	19.354s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	19.190s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	20.393s		0	1	0.00
		chip_sw_kmac_mode_kmac	19.792s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	19.247s		0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	19.792s		0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	19.735s		0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.661s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	19.786s		0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.587s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.587s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	15.687s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	15.288s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	15.453s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	19.792s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	20.393s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	30.702s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	31.975s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	30.537s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	30.537s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	30.537s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	31.127s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	18.864s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	18.864s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	19.243s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.621s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.529s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	10.280s		0	1	0.00
		chip_sw_data_integrity_escalation	10.131s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	31.127s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	19.792s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	19.243s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	16.344s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	31.127s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	19.792s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	19.243s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	16.344s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	15.607s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.430s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.326s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.070s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.611s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.508s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.135s		0	1	0.00
		chip_prim_tl_access	32.135s		0	1	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	32.135s		0	1	0.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.139s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.135s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.266s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	31.975s		0	1	0.00
		chip_sw_aes_enc_jitter_en	27.996s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	19.354s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	20.393s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	19.247s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.621s		0	1	0.00
		chip_sw_clkmgr_jitter	15.828s		0	1	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	31.096s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	31.096s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	33.216s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	32.731s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	30.867s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	31.074s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	31.603s		0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	16.337s		0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	16.344s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	14.798s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	14.798s		0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	52.019s		0	1	0.00
		chip_sw_aon_timer_smoketest	49.714s		0	1	0.00
		chip_sw_clkmgr_smoketest	49.765s		0	1	0.00
		chip_sw_csrng_smoketest	50.974s		0	1	0.00
		chip_sw_gpio_smoketest	50.703s		0	1	0.00
		chip_sw_hmac_smoketest	50.026s		0	1	0.00
		chip_sw_kmac_smoketest	49.708s		0	1	0.00
		chip_sw_otbn_smoketest	50.735s		0	1	0.00
		chip_sw_otp_ctrl_smoketest	49.851s		0	1	0.00
		chip_sw_rv_plic_smoketest	50.360s		0	1	0.00
		chip_sw_rv_timer_smoketest	49.106s		0	1	0.00
		chip_sw_rstmgr_smoketest	50.196s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	48.093s		0	1	0.00
		chip_sw_uart_smoketest	47.754s		0	1	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	52.334s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	50.884s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	16.848s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	16.270s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	10.608s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	10.603s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	10.755s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	14.777s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	14.154s		0	1	0.00
		chip_rv_dm_lc_disabled	12.442m	19.254ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	16.503s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.051s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	14.621s		0	1	0.00
		chip_sw_lc_walkthrough_rma	16.031s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	14.154s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	15.651s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	15.336s		0	1	0.00
		rom_volatile_raw_unlock	11.577s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.752s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	14.877s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	15.095s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.993m	3.327ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.993m	3.327ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	7.830s		0	1	0.00
		chip_same_csr_outstanding	7.850s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	7.830s		0	1	0.00
		chip_same_csr_outstanding	7.850s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.231m	75.952us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.040s	13.120us	1	1	100.00
		xbar_smoke_large_delays	4.227m	2.454ms	1	1	100.00
		xbar_smoke_slow_rsp	32.702s		0	1	0.00
		xbar_random_zero_delays	46.300s	48.161us	1	1	100.00
		xbar_random_large_delays	19.726m	11.987ms	1	1	100.00
		xbar_random_slow_rsp	9.947m	4.174ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	34.300s	29.498us	1	1	100.00
		xbar_error_and_unmapped_addr	1.050m	160.326us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.590m	304.489us	1	1	100.00
		xbar_error_and_unmapped_addr	1.050m	160.326us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	30.830s	34.706us	1	1	100.00
		xbar_access_same_device_slow_rsp	36.523s		0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	56.970s	67.799us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	14.034m	2.611ms	1	1	100.00
		xbar_stress_all_with_error	1.086m	236.795us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.807m	200.707us	1	1	100.00
		xbar_stress_all_with_reset_error	11.438m	1.556ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.184s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.696s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.739s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.697s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.698s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.749s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.677s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.835s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.784s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.150s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.876s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.812s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.810s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.329s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	15.570s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.847s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	15.463s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.370s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.253s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.216s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.245s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.247s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.515s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.144s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.897s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	14.072s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.545s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.661s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.177s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.399s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	10.699s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	10.849s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	10.901s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	10.649s		0	1	0.00
		rom_e2e_asm_init_dev	10.701s		0	1	0.00
		rom_e2e_asm_init_prod	10.954s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.482s		0	1	0.00
		rom_e2e_asm_init_rma	10.893s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.951s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.111s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.062s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.944s		0	1	0.00
V2		TOTAL			16	205	7.80
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	16.555s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	15.360s		0	1	0.00
V2S		TOTAL			0	2	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.003s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.789s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.080s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.571s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	10.280s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	13.578s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	13.089s		0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	18.307s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.631s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.003s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.789s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.080s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.428s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.993s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.994s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	45.812s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	10.030s		0	1	0.00
		chip_sw_entropy_src_kat_test	14.267s		0	1	0.00
		chip_sw_entropy_src_ast_rng_req	14.703s		0	1	0.00
		chip_plic_all_irqs_0	19.723s		0	1	0.00
		chip_plic_all_irqs_10	18.199s		0	1	0.00
		chip_sw_dma_inline_hashing	15.843s		0	1	0.00
		chip_sw_dma_abort	14.698s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.789s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.971s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.805s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.814s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.814s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.914s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.964s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.760s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.021s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.752s		0	1	0.00
		chip_sw_entropy_src_smoketest	49.767s		0	1	0.00
		chip_sw_mbx_smoketest	50.223s		0	1	0.00
		TOTAL			17	250	6.80

Failure Buckets

Job returned non-zero exit code has 226 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.41130342524647913542196069403562300302019067099852697334687718713798232459081
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

              done; \
          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_test_from_rom_sim_dv".
  Building "//sw/device/tests:example_test_from_rom_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_rom_sim_dv
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.111631568639676681601671206706763488344396957179499772103947280005198367802875
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "@manufacturer_test_hooks//:example_test_sim_dv".
  Building "@manufacturer_test_hooks//:example_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true @manufacturer_test_hooks//:example_test_sim_dv
  Another command (pid=896529) is running. Waiting for it to complete on the server (server_pid=892316)...
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_example_concurrency has 1 failures.

0.chip_sw_example_concurrency.95875478097810657634487335584842413508687953148133705802524050255392254657463
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_concurrency_test_sim_dv".
  Building "//sw/device/tests:example_concurrency_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_concurrency_test_sim_dv
  Another command (pid=896529) is running. Waiting for it to complete on the server (server_pid=892316)...
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_all_escalation_resets has 1 failures.

0.chip_sw_all_escalation_resets.2114235456546809945062982887624789240965443257027913959824932861942492382334
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

              done; \
          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv".
  Building "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.64652666712259410201163154196383178260363498516127847508432663046183558185696
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

              done; \
          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv".
  Building "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

... and 221 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.38696364044090420263621727054183209851818431040674950459097047848186642387337
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.105297234560698939135509894410945742280665931641101905441650928062726542898935
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.87429960793289933818009445759178596237548342788034495937941517441092572740240
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.77592243066930488019889735586645772832567682012221208375234417976526009407616
Line 6272, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4990.630482 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'hdadd1ab  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h1  a_user: 'h248bf  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4990.630482 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.86204643216589656133420733065169991379865353283489228090914352965080934932442
Line 6272, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3658.048803 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'hf59e29e8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h0  a_user: 'h26940  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3658.048803 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.72178867247950885321436472836555753141105742704755968841483326276894641453134
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3326.988570 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3326.988570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.54399523202932907272297737778015078205654494102825387745824597361882459799410
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```